Numerical Methods for Scientists and Engineers

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Detection, Estimation, and Modulation Theory

Microsoft Kinect, a low-cost motion sensing device, enables users to interact with computers or game consoles naturally through gestures and spoken commands without any other peripheral equipment. As such, it has commanded intense interests in research and development on the Kinect technology. In this paper, we present, a comprehensive survey on Kinect applications, and the latest research and development on motion recognition using data captured by the Kinect sensor. On the applications front, we review the applications of the Kinect technology in a variety of areas, including healthcare, education and performing arts, robotics, sign language recognition, retail services, workplace safety training, as well as 3D reconstructions. On the technology front, we provide an overview of the main features of both versions of the Kinect sensor together with the depth sensing technologies used, and review literatures on human motion recognition techniques used in Kinect applications. We provide a classification of motion recognition techniques to highlight the different approaches used in human motion recognition. Furthermore, we compile a list of publicly available Kinect datasets. These datasets are valuable resources for researchers to investigate better methods for human motion recognition and lower-level computer vision tasks such as segmentation, object detection and human pose estimation.

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A Survey of Applications and Human Motion Recognition with Microsoft Kinect

IEEE transactions on very large scale integration (VLSI) systems

This paper presents a novel convolutional neural network (CNN) -based method for high-accuracy real-time car license plate detection. Many contemporary methods for car license plate detection are reasonably effective under the specific conditions or strong assumptions only. However, they exhibit poor performance when the assessed car license plate images have a degree of rotation, as a result of manual capture by traffic police or deviation of the camera. Therefore, we propose the a CNN-based MD-YOLO framework for multi-directional car license plate detection. Using accurate rotation angle prediction and a fast intersection-over-union evaluation strategy, our proposed method can elegantly manage rotational problems in real-time scenarios. A series of experiments have been carried out to establish that the proposed method outperforms over other existing state-of-the-art methods in terms of better accuracy and lower computational cost.

A New CNN-Based Method for Multi-Directional Car License Plate Detection

Traffic sign recognition (TSR), taken as an important component of an intelligent vehicle system, has been an emerging research topic in recent years. In this paper, a traffic sign detection system based on color segmentation, speeded-up robust features (SURF) detection and the k-nearest neighbor classifier is introduced. The proposed system benefits from the SURF detection algorithm, which achieves invariance to rotated, skewed and occluded signs. In addition to the accuracy and robustness issues, a TSR system should target a real-time implementation on an embedded system. Therefore, a hardware/software co-design architecture for a Zynq-7000 FPGA is presented as a major objective of this work. The sign detection operations are accelerated by programmable hardware logic that searches the potential candidates for sign classification. Sign recognition and classification uses a feature extraction and matching algorithm, which is implemented as a software component that runs on the embedded ARM CPU.

/pdf/hardware-software-co-design-of-a-traffic-sign-recognition-3d6mgwmdcg.pdf

Hardware/Software Co-Design of a Traffic Sign Recognition System Using Zynq FPGAs

The decimal arithmetic has been receiving an increased attention because of the growth of financial and scientific applications requiring high precision and increased computing power. This paper presents an efficient architecture for multi-digit decimal addition based on carry-free signed-digit numbers. In this study, the decimal adder architecture has been designed and synthesized using the TSMC 0.18mu technology. The synthesis results were compared to the existing decimal adders with respect to design area, delay and power consumption. These results show that proposed adder architecture improves the area-delay factor by 3 for a 32 digit adder.

Design and Synthesis of a Carry-Free Signed-Digit Decimal Adder

In this work, a Convolutional Neural Network (CNN) architecture with a novel feature selector based on Wavelet Packets (WP) is introduced for ultrasonic flaw detection applications. CNN is among the key Deep Learning algorithms that have gained increased attention in recent years due to their success in machine vision, pattern recognition and classification tasks. CNN consists of multiple layers and it can extract features in a hierarchical manner to construct a high-level abstraction of the original data. We propose two CNN architectures (based on ID-CNN and LeNet models) for ultrasonic data (A-scan) using wavelet coefficients as feature inputs and investigate key topologies such as number of parallel convolution networks, number of filters and output classifiers. Optimal selection of wavelet subbands enables the CNN based model to detect the presence or the absence of flaws with an accuracy of up to 92% on experimental ultrasonic data.

A Multi-Resolution Convolutional Neural Network Architecture for Ultrasonic Flaw Detection

In this study, an efficient addressing scheme for radix-4 FFT processor is presented. The proposed method uses extra registers to buffer and reorder the data inputs of the butterfly unit. It avoids the modulo-r addition in the address generation; hence, the critical path is significantly shorter than the conventional radix-4 FFT implementations. A significant property of the proposed method is that the critical path of the address generator is independent from the FFT transform length N, making it extremely efficient for large FFT transforms. For performance evaluation, the new FFT architecture has been implemented by FPGA (Altera Stratix) hardware and also synthesized by CMOS 0.18µm technology. The results confirm the speed and area advantages for large FFTs. Although only radix-4 FFT address generation is presented in the paper, it can be used for higher radix FFT.

Fast memory addressing scheme for radix-4 FFT implementation

In this work, a Support Vector Machine (SVM) classifier is introduced for ultrasonic flaw detection based on features extracted from the output of the subband decomposition filters. SVM is a machine learning method used for classification and regression analysis of complex real-world problems that may be difficult to analyze theoretically. A dataset constituting feature vectors of ultrasonic signals containing flaw and no flaw, is created in order to train and test the SVM. A k-fold cross validation technique is then performed to choose the best parameters for classification. Experimental results, using A-scan data measurements from a steel block, show that a very high classification accuracy can be achieved. Robust performance of the classifier is due to proper selection of frequency-diverse feature vectors and successful training.

Erdal Oruklu

Papers

Hardware/Software Co-Design of a Traffic Sign Recognition System Using Zynq FPGAs

Design and Synthesis of a Carry-Free Signed-Digit Decimal Adder

A Multi-Resolution Convolutional Neural Network Architecture for Ultrasonic Flaw Detection

Fast memory addressing scheme for radix-4 FFT implementation

Ultrasonic flaw detection using Support Vector Machine classification