This survey presents an overview of recent advances in the state of the art for computer-aided design (CAD) tools for analog and mixed-signal integrated circuits (ICs). Analog blocks typically constitute only a small fraction of the components on mixed-signal ICs and emerging systems-on-a-chip (SoC) designs. But due to the increasing levels of integration available in silicon technology and the growing requirement for digital systems to communicate with the continuous-valued external world, there is a growing need for CAD tools that increase the design productivity and improve the quality of analog integrated circuits. This paper describes the motivation and evolution of these tools and outlines progress on the various design problems involved: simulation and modeling, symbolic analysis, synthesis and optimization, layout generation, yield analysis and design centering, and test. This paper summarizes the problems for which viable solutions are emerging and those which are still unsolved.

/pdf/computer-aided-design-of-analog-and-mixed-signal-integrated-23xbvj9rc2.pdf

Computer-aided design of analog and mixed-signal integrated circuits

We describe a new method for determining component values and transistor dimensions for CMOS operational amplifiers (op-amps). We observe that a wide variety of design objectives and constraints have a special form, i.e., they are posynomial functions of the design variables. As a result, the amplifier design problem can be expressed as a special form of optimization problem called geometric programming, for which very efficient global optimization methods have been developed. As a consequence we can efficiently determine globally optimal amplifier designs or globally optimal tradeoffs among competing performance measures such as power, open-loop gain, and bandwidth. Our method, therefore, yields completely automated sizing of (globally) optimal CMOS amplifiers, directly from specifications. In this paper, we apply this method to a specific widely used operational amplifier architecture, showing in detail how to formulate the design problem as a geometric program. We compute globally optimal tradeoff curves relating performance measures such as power dissipation, unity-gain bandwidth, and open-loop gain. We show how the method can he used to size robust designs, i.e., designs guaranteed to meet the specifications for a variety of process conditions and parameters.

/pdf/optimal-design-of-a-cmos-op-amp-via-geometric-programming-4thsejbwi6.pdf

Optimal design of a CMOS op-amp via geometric programming

Analog synthesis tools have traditionally traded quality for speed, substituting simplified circuit evaluation methods for full simulation in order to accelerate the numerical search for solution candidates. As a result, these tools have failed to migrate into mainstream use primarily because of difficulties in reconciling the simplified models required for synthesis with the industrial-strength simulation environments required for validation. We argue that for synthesis to be practical, it is essential to synthesize a circuit using the same simulation environment created to validate the circuit. In this paper, we develop a new numerical search algorithm efficient enough to allow full circuit simulation of each circuit candidate, and robust enough to find good solutions for difficult circuits. The method combines the population-of-solutions ideas from evolutionary algorithms with a novel variant of pattern search, and supports transparent network parallelism. Comparison of several synthesized cell-level circuits against manual industrial designs demonstrates the utility of the approach.

/pdf/anaconda-simulation-based-synthesis-of-analog-circuits-via-1n002nltqu.pdf

Anaconda: simulation-based synthesis of analog circuits via stochastic pattern search

The paper describes the recent state of the art in hierarchical analog synthesis, with a strong emphasis on associated techniques for computer-aided model generation and optimization. Over the past decade, analog design automation has progressed to the point where there are industrially useful and commercially available tools at the cell level-tools for analog components with 10-100 devices. Automated techniques for device sizing, for layout, and for basic statistical centering have been successfully deployed. However, successful component-level tools do not scale trivially to system-level applications. While a typical analog circuit may require only 100 devices, a typical system such as a phase-locked loop, data converter, or RF front-end might assemble a few hundred such circuits, and comprise 10 000 devices or more. And unlike purely digital systems, mixed-signal designs typically need to optimize dozens of competing continuous-valued performance specifications, which depend on the circuit designer's abilities to successfully exploit a range of nonlinear behaviors across levels of abstraction from devices to circuits to systems. For purposes of synthesis or verification, these designs are not tractable when considered "flat." These designs must be approached with hierarchical tools that deal with the system's intrinsic design hierarchy. This paper surveys recent advances in analog design tools that specifically deal with the hierarchical nature of practical analog and RF systems. We begin with a detailed survey of algorithmic techniques for automatically extracting a suitable nonlinear macromodel from a device-level circuit. Such techniques are critical to both verification and synthesis activities for complex systems. We then survey recent ideas in hierarchical synthesis for analog systems and focus in particular on numerical techniques for handling the large number of degrees of freedom in these designs and for exploring the space of performance tradeoffs early in the design process. Finally, we briefly touch on recent ideas for accommodating models of statistical manufacturing variations in these tools and flows

Hierarchical Modeling, Optimization, and Synthesis for System-Level Analog and RF Designs

The paper describes the recent state of the art in hierarchy. This paper surveys recent advances in analog design tools that specifically deal with the hierarchical nature of practical analog and RF systems. We begin with a detailed survey of algorithmic techniques for automatically extracting a suitable nonlinear macromodel from a device-level circuit. Such techniques are critical to both verification and synthesis activities for complex systems. We then survey recent ideas in hierarchical synthesis for analog systems and focus in particular on numerical techniques for handling the large number of degrees of freedom in these designs and for exploring the space of performance tradeoffs early in the design process. Finally, we briefly touch on recent ideas for accommodating models of statistical manufacturing variations in these tools and flows.

/pdf/hierarchical-modeling-optimization-and-synthesis-for-system-h6f6gtng0x.pdf

Hierarchical Modeling, Optimization, and Synthesis for System-Level Analog and RF Designs Small models, that represent the overall functioning of portions of large or complex circuits, can be generated by algorithms and used for system design and verification.

A synthesis environment for analog integrated circuits is presented that is able to drastically increase design and layout productivity for analog blocks. The system covers the complete design flow from specification over topology selection and optimal circuit sizing down to automatic layout generation and performance characterization. It follows a hierarchical refinement strategy for more complex cells and is process independent. The sizing is based on an improved equation-based optimization approach, where the circuit behavior is characterized by declarative models that are then converted in a sequential design plan. Supporting tools have been developed to reduce the total effort to set up a new circuit topology in the system's database. The performance-driven layout generation tool guarantees layouts that satisfy all performance constraints. Redesign support is included in the design flow management to perform backtracking in case of design problems. The experimental results illustrate the productiveness and efficiency of the environment for the synthesis and process tuning of frequently used analog cells.

AMGIE-A synthesis environment for CMOS analog integrated circuits

This paper discusses the realization of an analogue module generator that forms part of a mixed analogue/digital design environment. It is able to design analogue functional modules such as like amplifiers, filters, etc., either in an automatic or in an interactive session, starting from performance specifications over topology selection, parameter optimization and simulation/verification down to lay-out. the analogue module generator is integrated in a commercial EDA framework. Practical design results show the capabilities and efficiency of the system.

An analogue module generator for mixed analogue/digital asic design

This paper describes a new modeling methodology that allows to derive systematically behavioral signal path models of operational amplifiers. Combined with symbolic simulation, these models provide high qualitative insight in the small-signal functioning of a circuit. The behavioral signal path model provides compact interpretable expressions for the poles and zeros that constitute the signal path. These expressions show which design parameters have dominant influence on the position of a pole/zero and thus enable a designer to control a manual interactive sizing process. The methodology consists of the application of a sequence of abstractions, so that one gradually progresses from a full device to a full behavior circuit representation. During this translation, qualitative insight and design requirements are obtained. The methodology is implemented in an open tool called \EFtoef. The behavioral signal path model is also used for optimization based sizing in order to achieve pole placement in an efficient way. For optimization based sizing, a new strategy for hierarchical penalty function composition is proposed, which allows sequential pruning of the design space. Combined with an operating point driven \DC formulation and local minimax optimization, a fast sizing method is obtained which can be used for interactive design space exploration. Experimental results of both modeling and sizing are shown.

/pdf/a-behavioral-signal-path-modeling-methodology-for-zyvwga3ezz.pdf

A behavioral signal path modeling methodology for qualitative insight in and efficient sizing of CMOS opamps

The task of a topology selector within an analog synthesis system is to find the best available analog circuit topology out of a library for a given set of input specification. The proposed selection method consists of a combination of two approaches: procedural filtering and rule-based filtering. The procedural filtering consists of two consecutive phases based on boundary checking and interval analysis. Such a combination of different sorts of filtering is a new technique that allows an optimal trade-off between selection accuracy and required selection time. The tool that implements the method is technology independent and fully open towards newly added design knowledge. >

/pdf/a-flexible-topology-selection-program-as-part-of-an-analog-274mnt6zhw.pdf

A flexible topology selection program as part of an analog synthesis system

This paper describes the transformation of small-signal modeling of analog integrated circuits into control system modeling. Transforming a small-signal circuit into a control system equivalent results in a behavioral signal path (BSP) model. A BSP model gives insight in the operation of a circuit because it shows all the different conversions from current to voltage and vice versa, including poles and zeros which cause a decrease-increase in transfer along the signal path. The different poles are a function of the small-signal parameters of the different devices and are modeled with small symbolic equations, which make them fully comprehensible. This enables the designer to accurately control the sizing process by enabling pole/zero placement. On a BSP model, all theorems of control theory as well as typical design approximations can be performed. The methodology and its applications are illustrated with several examples.

F. Leyn

Papers

AMGIE-A synthesis environment for CMOS analog integrated circuits

An analogue module generator for mixed analogue/digital asic design

A behavioral signal path modeling methodology for qualitative insight in and efficient sizing of CMOS opamps

A flexible topology selection program as part of an analog synthesis system

Analog small-signal modeling-part I: behavioral signal path modeling for analog integrated circuits