An experimental technique is described for observing the effects of switching transients in digital MOS circuits that perturb analog circuits integrated on the same die by means of coupling through the substrate Various approaches to reducing substrate crosstalk (the use of physical separation of analog and digital circuits, guard rings, and a low-inductance substrate bias) are evaluated experimentally for a CMOS technology with a substrate comprising an epitaxial layer grown on a heavily doped bulk wafer Observations indicate that reducing the inductance in the substrate bias is the most effective Device simulations are used to show how crosstalk propagates via the heavily doped bulk and to predict the nature of substrate crosstalk in CMOS technologies integrated in uniform, lightly doped bulk substrates, showing that in such cases the substrate noise is highly dependent on layout geometry A method of including substrate effects in SPICE simulations for circuits fabricated on epitaxial, heavily doped substrates is developed >

Experimental Results and Modeling Techniques for Substrate Noise in Mixed-Signal Integrated Circuits

In this paper, a 10-bit 1-GSample/s current-steering CMOS digital-to-analog (D/A) converter is presented. The measured integral nonlinearity is better than /spl plusmn/0.2 LSB and the measured differential nonlinearity lies between -0.08 and 0.14 LSB proving the 10-bit accuracy. The 1-GSample/s conversion rate has been obtained by an, at transistor level, fully custom-designed thermometer decoder and synchronization circuit. The layout has been carefully optimized. The parasitic interconnect loads have been estimated and have been iterated in the circuit design. A spurious-free dynamic range (SFDR) of more than 61 dB has been measured in the interval from dc to Nyquist. The power consumption equals 110 mW for a near-Nyquist sinusoidal output signal at a 1-GHz clock. The chip has been processed in a standard 0.35-/spl mu/m CMOS technology and has an active area of only 0.35 mm/sup 2/.

A 10-bit 1-GSample/s Nyquist current-steering CMOS D/A converter

CMOS Data Converters for Communications distinguishes itself from other data converter books by emphasizing system-related aspects of the design and frequency-domain measures. It explains in detail how to derive data converter requirements for a given communication system (baseband, passband, and multi-carrier systems). The authors also review CMOS data converter architectures and discuss their suitability for communications. The rest of the book is dedicated to high-performance CMOS data converter architecture and circuit design. Pipelined ADCs, parallel ADCs with an improved passive sampling technique, and oversampling ADCs are the focus for ADC architectures, while current-steering DAC modeling and implementation are the focus for DAC architectures. The principles of the switched-current and the switched-capacitor techniques are reviewed and their applications to crucial functional blocks such as multiplying DACs and integrators are detailed. The book outlines the design of the basic building blocks such as operational amplifiers, comparators, and reference generators with emphasis on the practical aspects. To operate analog circuits at a reduced supply voltage, special circuit techniques are needed. Low-voltage techniques are also discussed in this book. CMOS Data Converters for Communications can be used as a reference book by analog circuit designers to understand the data converter requirements for communication applications. It can also be used by telecommunication system designers to understand the difficulties of certain performance requirements on data converters. It is also an excellent resource to prepare analog students for the new challenges ahead.

CMOS Data Converters for Communications

In this paper, a 14-bit, 150-MSamples/s current steering digital-to-analog converter (DAC) is presented. It uses the novel Q/sup 2/ random walk switching scheme to obtain full 14-bit accuracy without trimming or tuning. The measured integral and differential nonlinearity performances are 0.3 and 0.2 LSB, respectively; the spurious-free dynamic range is 84 dB at 500 kHz and 61 dB at 5 MHz. Running from a single 2.7-V power supply, it has a power consumption of 70 mW for an input signal of 500 kHz and 300 mW for an input signal of 15 MHz. The DAC has been integrated in a standard digital single-poly, triple-metal 0.5-/spl mu/m CMOS process. The die area is 13.1 mm/sup 2/.

A 14-bit intrinsic accuracy Q/sup 2/ random walk CMOS DAC

The paper describes the recent state of the art in hierarchical analog synthesis, with a strong emphasis on associated techniques for computer-aided model generation and optimization. Over the past decade, analog design automation has progressed to the point where there are industrially useful and commercially available tools at the cell level-tools for analog components with 10-100 devices. Automated techniques for device sizing, for layout, and for basic statistical centering have been successfully deployed. However, successful component-level tools do not scale trivially to system-level applications. While a typical analog circuit may require only 100 devices, a typical system such as a phase-locked loop, data converter, or RF front-end might assemble a few hundred such circuits, and comprise 10 000 devices or more. And unlike purely digital systems, mixed-signal designs typically need to optimize dozens of competing continuous-valued performance specifications, which depend on the circuit designer's abilities to successfully exploit a range of nonlinear behaviors across levels of abstraction from devices to circuits to systems. For purposes of synthesis or verification, these designs are not tractable when considered "flat." These designs must be approached with hierarchical tools that deal with the system's intrinsic design hierarchy. This paper surveys recent advances in analog design tools that specifically deal with the hierarchical nature of practical analog and RF systems. We begin with a detailed survey of algorithmic techniques for automatically extracting a suitable nonlinear macromodel from a device-level circuit. Such techniques are critical to both verification and synthesis activities for complex systems. We then survey recent ideas in hierarchical synthesis for analog systems and focus in particular on numerical techniques for handling the large number of degrees of freedom in these designs and for exploring the space of performance tradeoffs early in the design process. Finally, we briefly touch on recent ideas for accommodating models of statistical manufacturing variations in these tools and flows

Hierarchical Modeling, Optimization, and Synthesis for System-Level Analog and RF Designs

A synthesis environment for analog integrated circuits is presented that is able to drastically increase design and layout productivity for analog blocks. The system covers the complete design flow from specification over topology selection and optimal circuit sizing down to automatic layout generation and performance characterization. It follows a hierarchical refinement strategy for more complex cells and is process independent. The sizing is based on an improved equation-based optimization approach, where the circuit behavior is characterized by declarative models that are then converted in a sequential design plan. Supporting tools have been developed to reduce the total effort to set up a new circuit topology in the system's database. The performance-driven layout generation tool guarantees layouts that satisfy all performance constraints. Redesign support is included in the design flow management to perform backtracking in case of design problems. The experimental results illustrate the productiveness and efficiency of the environment for the synthesis and process tuning of frequently used analog cells.

AMGIE-A synthesis environment for CMOS analog integrated circuits

A 12-bit 200 MHz CMOS current steering D/A converter is presented. The measured glitch energy is 0.8 pVs. To obtain this very low glitch energy specification, a new driver circuit using a dynamic latch is proposed. The measured INL is better than +/-0.5 LSB. The D/A converter operates at a 2.7 V power supply, it has a 20 mA full swing output current and a 200 MHz conversion rate. The worst case power consumption is 140 mW at the maximum conversion rate. The chip has been processed in a standard 0.5 /spl mu/m CMOS technology.

A 12 bit 200 MHz low glitch CMOS D/A converter

The design issues and tradeoffs of a high-speed high-accuracy Nyquist-rate analog-to-digital (A/D) converter are described. The presented design methodology covers the complete flow from specifications to verified layout and is supported by both commercial and internally developed computer-aided design tools. The major decisions to be made during the converter's design at both the architectural and the circuit level are described and the tradeoffs are elaborated. The approach is demonstrated for a real-life test case, where a Nyquist-rate 8-bit 200-MS/s 4-2 interpolating/averaging A/D converter was developed in a 0.35-/spl mu/m CMOS technology. The signal-to-noise-plus-distortion ratio at 40 MHz is 42.7 dB and the total power consumption is 655 mW.

Design techniques and implementation of an 8-bit 200-MS/s interpolating/averaging CMOS A/D converter

This brief presents a systematic design methodology for digital-to analog (D/A) converter macrocells for integrated VLSI systems. A generic behavioral model is included for system level exploration to define the converter's specifications. The architecture and the sizes of the devices are then calculated using a performance-driven design methodology. Using a novel layout tool, the layout of the regular structures with complex connectivity, typical for D/A converters, is automatically generated. Finally, a detailed behavioral model is extracted, combining both complex dynamic behavior (glitch energy) and static behavior. A 12-bit and two 14-bit D/A converters have been designed using this approach. It is demonstrated how the applied methodology and supporting tools drastically reduce the total design time, thereby significantly increasing analog design productivity.

J. Vandenbussche

Papers

A 14-bit intrinsic accuracy Q/sup 2/ random walk CMOS DAC

AMGIE-A synthesis environment for CMOS analog integrated circuits

A 12 bit 200 MHz low glitch CMOS D/A converter

Design techniques and implementation of an 8-bit 200-MS/s interpolating/averaging CMOS A/D converter

Systematic design of high-accuracy current-steering D/A converter macrocells for integrated VLSI systems