A program to numerically simulate quantum transport in double gate metal oxide semiconductor field effect transistors (MOSFETs) is described. The program uses a Green's function approach and a simple treatment of scattering based on the idea of so-called Buttiker probes. The double gate device geometry permits an efficient mode space approach that dramatically lowers the computational burden and permits use as a design tool. Also implemented for comparison are a ballistic solution of the Boltzmann transport equation and the drift-diffusion approaches. The program is described and some examples of the use of nanoMOS for 10 nm double gate MOSFETs are presented.

nanoMOS 2.5: A two-dimensional simulator for quantum transport in double-gate MOSFETs

We describe the implementation of a Monte Carlo model for electron transport in silicon. The model uses analytic, nonparabolic electron energy bands, which are computationally efficient and sufficiently accurate for future low-voltage s, 1V d nanoscale device applications. The electron-lattice scattering is incorporated using an isotropic, analytic phonon-dispersion model, which distinguishes between the optical/acoustic and the longitudinal/transverse phonon branches. We show that this approach avoids introducing unphysical thresholds in the electron distribution function, and that it has further applications in computing detailed phonon generation spectra from Joule heating. A set of deformation potentials for electron-phonon scattering is introduced and shown to yield accurate transport simulations in bulk silicon across a wide range of electric fields and temperatures. The shear deformation potential is empirically determined at Ju= 6.8 eV, and consequently, the isotropically averaged scattering potentials with longitudinal and transverse acoustic phonons are DLA= 6.39 eV and DTA= 3.01 eV, respectively, in reasonable agreement with previous studies. The room-temperature electron mobility in strained silicon is also computed and shown to be in better agreement with the most recent phonon-limited data available. As a result, we find that electron coupling with g-type phonons is about 40% lower, and the coupling with f-type phonons is almost twice as strong as previously reported. © 2004 American Institute of Physics . [DOI: 10.1063/1.1788838]

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Analytic band Monte Carlo model for electron transport in Si including acoustic and optical phonon dispersion

Variations in process parameters affect the operation of integrated circuits (ICs) and pose a significant threat to the continued scaling of transistor dimensions. Such parameter variations, however, tend to affect logic and memory circuits in different ways. In logic, this fluctuation in device geometries might prevent them from meeting timing and power constraints and degrade the parametric yield. Memories, on the other hand, experience stability failures on account of such variations. Process limitations are not exhibited as physical disparities only; transistors experience temporal device degradation as well. Such issues are expected to further worsen with technology scaling. Resolving the problems of traditional Si-based technologies by employing non-Si alternatives may not present a viable solution; the non-Si miniature devices are expected to suffer the ill-effects of process/temporal variations as well. To circumvent these nonidealities, there is a need to design ICs that can adapt themselves to operate correctly under the presence of such inconsistencies. In this paper, we first provide an overview of the process variations and time-dependent degradation mechanisms. Next, we discuss the emerging paradigm of variation-tolerant adaptive design for both logic and memories. Interestingly, these resiliency techniques transcend several design abstraction levels-we present circuit and microarchitectural techniques to perform reliable computations in an unreliable environment.

Parameter Variation Tolerance and Error Resiliency: New Design Paradigm for the Nanoscale Era

The purpose of this review article is to report on the recent developments and the performance level achieved in the strained-Si/SiGe material system. In the first part, the technology of the growth of a high-quality strained-Si layer on a relaxed, linear or step-graded SiGe buffer layer is reviewed. Characterization results of strained-Si films obtained with secondary ion mass spectroscopy, Rutherford backscattering spectroscopy, atomic force microscopy, spectroscopic ellipsometry and Raman spectroscopy are presented. Techniques for the determination of bandgap parameters from electrical characterization of metal-oxide-semiconductor (MOS) structures on strained-Si film are discussed. In the second part, processing issues of strained-Si films in conventional Si technology with low thermal budget are critically reviewed. Thermal and low-temperature microwave plasma oxidation and nitridation of strained-Si layers are discussed. Some recent results on contact metallization of strained-Si using Ti and Pt are presented. In the last part, device applications of strained Si with special emphasis on heterostructure metal oxide semiconductor field effect transistors and modulation-doped field effect transistors are discussed. Design aspects and simulation results of n- and p-MOS devices with a strained-Si channel are presented. Possible future applications of strained-Si/SiGe in high-performance SiGe CMOS technology are indicated.

http://iopscience.iop.org/article/10.1088/0268-1242/13/11/002/pdf

Strained-Si heterostructure field effect transistors

We propose a new experimental technique to study the transport properties of stress-induced leakage current (SILC). Based on the carrier separation measurement for p-channel MOSFETs, the quantum yield of impact ionization for electrons involved in the SILC process is evaluated directly from the change in the source and gate currents of p-MOSFETs before and after stressing. Since the relationship between the electron energy and the quantum yield is established for direct and FN tunneling currents, the electron energy of electrons involved in the SILC process can be determined from the quantum yield. The results reveal that the measured energy of electrons in the SILC process is lower roughly by 1.5 eV than the energy expected in the elastic tunneling process. Trap-assisted inelastic tunneling model is proposed as a conduction mechanism of SILC accompanied by energy relaxation. It is shown, through the evaluation of the substrate hole current in n-channel MOSFETs, that the contribution of trap-assisted valence electron tunneling, another possible mechanism to explain the energy relaxation, to SILC is small.

Experimental evidence of inelastic tunneling in stress-induced leakage current

An efficient self-consistent device simulator coupling Poisson equation and Monte Carlo transport suitable for general silicon devices, including those with regions of high doping/carrier densities, is discussed. Key features include an original iteration scheme and an almost complete vectorization of the program. The simulator has been used to characterize nonequilibrium effects in deep submicron nMOSFETs. Substantial overshoot effects are noticeable at gate lengths of 0.25 mu m at room temperatures. >

A general purpose device simulator coupling Poisson and Monte Carlo transport with applications to deep submicron MOSFETs

A new silicon model for electron transport at high electric fields is presented. The model features an original conduction-band structure consisting of three isotropic bands together with the lowest non-parabolic band in a finite spherical Brillouin zone. The bands are given by analytic expressions whose parameters are fixed by best fitting the density of states taken from band-structure calculations. Such a model is consistently used in electron dynamics and in the evaluation of the scattering probabilities. The coupling constants to the scattering agents are determined by best fitting the available experimental data on transport properties. The effect of the new model on the results is discussed for a bulk system with particular attention to the features (e.g. the detailed shape of the electron distribution function) which are important for device applications.

A many-band silicon model for hot-electron transport at high energies

An efficient Monte Carlo device simulator has been developed as a postprocessor of a two-dimensional numerical analyzer based on the drift-diffusion model. The Monte Carlo package analyzes real VLSI MOSFETs in a minicomputer environment, overcoming some existing theoretical and practical problems. In particular, the particle free-flight time distribution is obtained by a new algorithm, leading to a CPU time saving of at least one order of magnitude compared with the traditional approach. To describe rare electron configurations, such as the high-energy tails of the distributions and the particle dynamics in the presence of large retarding fields, a multiple repetition scheme was implemented. Selected applications are presented to illustrate the simulator's capabilities. >

MOS/sup 2/: an efficient MOnte Carlo Simulator for MOS devices

In this paper a quantitative study of the electron energy distribution in silicon devices at low applied voltages is carried out by means of Monte Carlo simulations including the main mechanisms involved in the process of carrier heating We present a clear-cut interpretation of the build up of the electron distribution at energies higher than that provided by the applied electric field (qV, V being the total voltage drop) Electron-electron interaction is analyzed and shown to be an effective process for the enhancement of the high-energy electron population

Hot carrier effects in short MOSFETs at low applied voltages

A study is presented on the effects of voltage scaling on hot-electron phenomena and intrinsic device performance in submicrometer MOSFETs. A Monte Carlo device simulator featuring a suitable band model for high-energy electrons is used. An interesting finding is that at very short channel lengths the high energy tail of the electron distribution function, the most important quantity in determining hot-carrier reliability, is controlled by the applied bias and not by local electric fields. As confirmed by recently reported experimental work, the results of this study indicate that the conventional, linear voltage scaling can be weakened using a more relaxed voltage reduction law that leads to improved performance without threatening device reliability. >

F. Venturi

Papers

A general purpose device simulator coupling Poisson and Monte Carlo transport with applications to deep submicron MOSFETs

A many-band silicon model for hot-electron transport at high energies

MOS/sup 2/: an efficient MOnte Carlo Simulator for MOS devices

Hot carrier effects in short MOSFETs at low applied voltages

The impact of voltage scaling on electron heating and device performance of submicrometer MOSFETs