An overview is presented of the significant influences of Moore’s Law scaling on radiation effects on microelectronics, focusing on historical trends and future needs. A number of milestones in the evolution and understanding of total-ionizing-dose and single-event effects are discussed within the context of classical Dennard scaling. This discussion focuses on the discovery of fundamental mechanisms, development of radiation-tolerant IC technology, and increasing maturity and complexity of Si-MOS-based devices, circuits, and systems. Examples are shown that illustrate how the end of Dennard scaling has influenced radiation effects in current technology generations, due to the increasingly complex and diverse materials and devices that are now incorporated. The radiation responses of devices with alternative channels to silicon and transistors based on 2-D materials are discussed, with an emphasis on opportunities and challenges for ultimately scaled devices. Particular challenges to ultimately scaled technologies are presented by single-particle-induced displacement damage and microdose effects. The article concludes with a look forward to a future in which many types of microelectronic devices and ICs are increasingly more vulnerable to radiation effects and increasingly more difficult to test in a practical and cost-effective manner.

Radiation Effects in a Post-Moore World

This paper provides a detailed description explaining how to calculate the relation between the silicon Raman frequency and local stress or strain in the silicon, applied to stress measurements in microelectronics. This relation is well known for measurements from the (100) surface of silicon. However, it is often used in the wrong way, neglecting non-zero stress tensor elements. Especially, in current 3D microelectronics technology, where the stress caused by through Si vias or micro-bumps is of large importance, the vertical stress component, which highly affects the measured Raman frequency shift, is often erroneously neglected. In addition, the equations for the (100) surface are also often used incorrectly for cross-sectional measurements from a (110) surface. In this paper, different ways to calculate the relation between Raman frequency and triaxial stress, and the related Raman peak intensities, are discussed in detail.

Relation between Raman frequency and triaxial stress in Si for surface and cross-sectional experiments in microelectronics components

Today 3D interconnection approaches are considered to provide one of the most promising enabling technologies for “More than Moore” solutions. In particular, 3D integration can provide significant progress in semiconductor device development regarding increased system functionality and integration density. In this paper, we describe an innovative concept for sensor integration based on a quality-proven “open” TSV technology on the basis of a 0.35μm CMOS process. An application-optimized sensor-layer is processed on a specific wafer substrate, whereas the CMOS circuits of the system can remain cost-efficiently on an appropriate 0.35μm CMOS or HV-CMOS technology. Another advantage of the proposed TSV solution is the geometric aspect. As the CMOS is attached to the sensor backside, almost 100% of the chip area can be used for the sensing functionality. In the presented technological approach, the sensor wafer is finalized with processing a top metal layer and successive bond oxide layers. The bond oxide layers are planarized by chemo mechanical polishing (CMP). The CMOS wafer is fabricated using a regular 0.35μm CMOS technology up to the vias before the last metal layer. A nitride layer is deposited in order to protect the integrated circuits from damages during the back grinding process. Prior to bonding, the CMOS wafer is thinned down to a thickness of 250μm and then bonded to the sensor wafer by plasma activated bonding followed by an annealing step to reinforce the bond strength. TSV etching is sequentially performed in three steps: firstly, the oxide of inter-metal dielectrics is opened. Secondly, the bulk silicon of the CMOS wafer is etched using a deep reactive ion etch (DRIE) process selectively stopping on the bond oxide of the sensor wafer. After several cleaning steps the spacer oxide is deposited followed by the spacer and bond oxide etching. For TSV metallisation, Tungsten as deposited in a CVD process is chosen providing uniform conformal coating inside the open TSVs. A sputtered Al forms the top metal and a subsequently produced passivation layer completes the fabrication process. With respect to the photo-lithography process for patterning the top metal and passivation layers, a specifically developed resist spray coating technique is used. This allows protecting the TSVs from damage due to the etching gases. The higher complexity of the lithography is compensated by a more simple and reliable processing regarding the TSV quality. The presented technological flow results in advantageous electrical properties of the TSV interconnects, e.g. low resistivity and a high breakdown voltage combined with excellent inherent reliability. The fabricated sensor devices were characterized by a variety of analytical techniques that have specifically been adapted to the requirements of 3D integrated wafer-bonded systems with TSVs. This approach allowed isolating, localizing and characterizing process related inhomogeneities and potential defects inside the open TSVs and in the wafer bond interface with improved analysis throughput. Electrical shorts of the TSV sidewall metallization to the Si substrate could be identified by Lock-in Thermography (LIT). The exact defect position at the sidewall could be estimated by applying a new defocusing technique to additionally determine the defect depth inside the TSV. As a consequence, the identified sidewall defects could subsequently be analyzed by high resolution transmission electron microscopy (HR TEM) to reveal their root causes. Scanning Acoustic Microscopy (SAM) with improved signal analysis and data evaluation was applied to identify and characterize local delamination defects in the wafer-bonded interface of the 3D sensor. The achieved progress regarding failure analysis methodology supported the technological developments and will contribute to secure quality and yield of 3D integrated devices during future manufacturing.

3D Sensor application with open through silicon via technology

This paper discusses mechanical stress measured with micro-Raman spectroscopy in the silicon substrate near Cu-Through Silicon Vias (TSV). A discussion of the relation between the observed Raman shift and the various stress tensor components is given, showing that this relation is often wrongly applied, and that in many cases the compressive stress along the vertical axis of the TSV, dominates the Raman results and hides the tensile axial component which is of most relevance for its impact on CMOS devices. The effect of measurement depth, TSV depth and density, and an oxide cap is shown. Both surface and cross-sectional results are discussed. Also a direct correlation between results from Raman measurements and electrical results from FET-arrays near a TSV is given.

In-depth Raman spectroscopy analysis of various parameters affecting the mechanical stress near the surface and bulk of Cu-TSVs

This paper focuses on the metrology needs and challenges of through-silicon via (TSV) fabrication, consisting of TSV etch, liner, barrier, and seed (L/B/S) depositions, copper plating, and copper chemical mechanical planarization. These TSVs, with typical dimensions within a factor of two or so of ≈5  μm  ×50  μm (diameter×depth ), present an innovative set of metrology challenges because of the high aspect ratio and large feature sizes. The metallization deposition process includes thin layers of L/B/S metal; metrology for these layers determines whether there is complete coverage of the sidewalls. Metrology for the fill step includes verifying that the TSVs are deposited without voids and that the extent of stress on the surrounding silicon does not exceed acceptable limits.

Metrology needs for through-silicon via fabrication

Mechanical strain/stress and crystal defects are produced in extremely thin wafers (thickness ∼10 µm) of 3D-LSIs not only during wafer thinning, but also after wafer bonding using fine-pitch, high-density microbumps and curing. Furthermore, the metal of through-Si via (TSV) and microbump not only becomes the cause of contamination, but also induces strain/stress (due to the difference in the co-efficient of thermal expansion (CTE) between Si and metal) in thinned Si substrate. X-ray photoelectron spectroscopy (XPS) results showed that the crystal quality of Si is highly deteriorated in the ultra-poly ground (UPG) surface after wafer thinning and stress relief. Micro-Raman spectroscopy (µRS) data revealed that a local tensile strain amount to 1.8 GPa was induced by 4×4 µm2 square sized Si microbumps in 10 µm-thick LSI wafers after bonding and curing. We have noticed that this locally induced strain/stress caused more than 10% change in the ON current of p-MOS transistor. CuSn microbumps have also induced strain/stress at Si wafer surface, and it penetrates deeper for larger bump size and wider for smaller bump pitch.

Wafer thinning, bonding, and interconnects induced local strain/stress in 3D-LSIs with fine-pitch high-density microbumps and through-Si vias

One of the most serious reliability issues, the local deformation produced in the stacked LSI die/wafer with respect to the die thickness and the sub-surface structures formed after several stress-relief methods are systematically and extensively studied. From the electron backscatter diffraction (EBSD) analysis, a more than one degree (>1°) of local misorientation is created in the stacked LSI Si around μ-bump region. This induces a large tensile stress above the μ-bump region and relatively small compressive stress in the bump-space region, which leads to an enhancement in the n-MOSFET mobility in the μ-bump region and decrease in mobility at bump-space region. As compared to CuSn system, the InAu μ-bump induced huge amount of tensile stress (> 300 MPa) in the stacked LSI die even for the bonding temperature of 200 °C. The groove structures or scratches found at the background surface after stress relief by plasma etching (PE) or Dry Polishing (DP) severely deteriorates the device characteristics after stacking, owing to the enhanced local deformation as against the stress relief method of chemical mechanical polishing (CMP). Even after 500 cycles of temperature cycle (TC) test, a 20 μm-width Cu-TSV array with 40- μm pitch values induces not only around −570 MPa of compressive stress in the stacked LSI die, but also a large variation in the induced stress values between different TSVs in the same array. For the LSI die/wafer thickness of anything less than 50 μm, the Young modulus (E) and Hardness (H) of the thinned die no longer behaves like a bulk single crystal Si, which severely increases the reliability risks in the highly integrated 3D-LSIs.

F. Yamada

Papers

Wafer thinning, bonding, and interconnects induced local strain/stress in 3D-LSIs with fine-pitch high-density microbumps and through-Si vias

Minimizing the local deformation induced around Cu-TSVs and CuSn/InAu-microbumps in high-density 3D-LSIs