다중혈관 관상동맥 환자에서 y-문합을 이용하여 양쪽 내흉동맥만을 사용한 우회술의 조기 성적

Advanced polyimide materials: Syntheses, physical properties and applications

Our understanding of the cellular implementation of systems-level neural processes like action, thought and emotion has been limited by the availability of tools to interrogate specific classes of neural cells within intact, living brain tissue. Here we identify and develop an archaeal light-driven chloride pump (NpHR) from Natronomonas pharaonis for temporally precise optical inhibition of neural activity. NpHR allows either knockout of single action potentials, or sustained blockade of spiking. NpHR is compatible with ChR2, the previous optical excitation technology we have described, in that the two opposing probes operate at similar light powers but with well-separated action spectra. NpHR, like ChR2, functions in mammals without exogenous cofactors, and the two probes can be integrated with calcium imaging in mammalian brain tissue for bidirectional optical modulation and readout of neural activity. Likewise, NpHR and ChR2 can be targeted together to Caenorhabditis elegans muscle and cholinergic motor neurons to control locomotion bidirectionally. NpHR and ChR2 form a complete system for multimodal, high-speed, genetically targeted, all-optical interrogation of living neural circuits.

Multimodal fast optical interrogation of neural circuitry

A mean-field phase diagram for conformationally symmetric diblock melts using the standard Gaussian polymer model is presented. Our calculation, which traverses the weak- to strong-segregation regimes, is free of traditional approximations. Regions of stability are determined for disordered (DIS) melts and for ordered structures including lamellae (L), hexagonally packed cylinders (H), body-centered cubic spheres (QIm3m), close-packed spheres (CPS), and the bicontinuous cubic network with Ia3d symmetry (QIa3d). The CPS phase exists in narrow regions along the order−disorder transition for χN ≥ 17.67. Results suggest that the QIa3d phase is not stable above χN ∼ 60. Along the L/QIa3d phase boundaries, a hexagonally perforated lamellar (HPL) phase is found to be nearly stable. Our results for the bicontinuous Pn3m cubic (QPn3m) phase, known as the OBDD, indicate that it is an unstable structure in diblock melts. Earlier approximation schemes used to examine mean-field behavior are reviewed, and compa...

Unifying Weak- and Strong-Segregation Block Copolymer Theories

Damascene copper electroplating for on-chip interconnections, a process that we conceived and developed in the early 1990s, makes it possible to fill submicron trenches and vias with copper without creating a void or a seam and has thus proven superior to other technologies of copper deposition. We discuss here the relationship of additives in the plating bath to superfilling, the phenomenon that results in superconformal coverage, and we present a numerical model which accounts for the experimentally observed profile evolution of the plated metal.

Damascene copper electroplating for chip interconnections

High density through silicon via (TSV) is a key in fabricating three-dimensional (3-D) large-scale integration (LSI). We have developed polycrystalline silicon (poly-Si) TSV technology and tungsten (W)/poly-Si TSV technology for 3-D integration. In the poly-Si TSV formation, low-pressure chemical vapor deposition poly-Si heavily doped with phosphorus was conformally deposited into the narrow and deep trench formed in a Si substrate after the surface of Si trench was thermally oxidized. In the W/poly-Si TSV formation, tungsten was deposited into the Si trench by atomic layer deposition method after the poly-Si deposition, where poly-Si was used as a liner layer for W deposition. The 3-D microprocessor test chip, 3-D memory test chip, 3-D image sensor chip, and 3-D artificial retina chip were successfully fabricated by using poly-Si TSV.

High-Density Through Silicon Vias for 3-D LSIs

High density through silicon via (TSV) is a key in fabricating three-dimensional (3-D) large-scale integration (LSI). We have developed polycrystalline silicon (poly-Si) TSV technology and tungsten (W)/poly-Si TSV technology for 3-D integration. In the poly-Si TSV formation, low-pressure chem- ical vapor deposition poly-Si heavily doped with phosphorus was conformally deposited into the narrow and deep trench formed in a Si substrate after the surface of Si trench was thermally oxidized. In the W/poly-Si TSV formation, tungsten was deposited into the Si trench by atomic layer deposition method after the poly-Si deposition, where poly-Si was used as a liner layer for W deposition. The 3-D microprocessor test chip, 3-D memory test chip, 3-D image sensor chip, and 3-D artificial retina chip were successfully fabricated by using poly-Si TSV.

High-Density Through Silicon Vias for 3-D LSIs : Silicon stacked chips that perform highly-parallel data transfer have been successfully fabricated for image processing, artificial retinas, and for microprocessor and memory testing

A three-dimensional (3-D) integration technology has been developed for the fabrication of a new 3-D shared-memory test chip. This 3-D technology is based on the wafer bonding and thinning method. Five key technologies for 3-D integration were developed, namely, the formation of vertical buried interconnections, metal microbump formations, stacked wafer thinning, wafer alignment, and wafer bonding. Deep trenches having a diameter of 2 mum and a depth of approximately 50 mum were formed in the silicon substrate using inductively coupled plasma etching to form vertical buried interconnections. These trenches were oxidized and filled with n+ polycrystalline silicon or tungsten. The 3-D devices and 3-D shared-memory test chips with three-stacked layers were fabricated by bonding the wafers with vertical buried interconnections after thinning. No characteristic degradation was observed in the fabricated 3-D devices. It was confirmed that fundamental memory operation and broadcast operation between the three memory layers could be successfully performed in the fabricated 3-D shared-memory test chip

Three-Dimensional Integration Technology Based on Wafer Bonding With Vertical Buried Interconnections

To achieve ultimate super chip integration, we have developed a three-dimensional integration technology called super-smart-stack technology using a self-assembly technique The chip alignment accuracy of within 1mum is obtained by the self-assembly technique We demonstrated for the first time that 3D SRAM test chip with ten memory layers was successfully fabricated using the super-smart-stack (SSS) technology

New three-dimensional integration technology using self-assembly technique

We have developed a new 3-D hybrid integration technology of complementary metal-oxide-semiconductors, microelectromechanical systems (MEMS), and photonics circuits for optoelectronic heterogeneous integrated systems. We have overcome the fabrication difficulties of optoelectromechanical and microfluidics hybrid integration. In order to verify the applied 3-D hybrid integration technology, we fabricated a 3-D optoelectronic multichip module composed of large-scale integration (LSI), MEMS, and photonics devices. The electrical chips of amplitude-shift keying (ASK) LSI, passive, and pressure-sensing MEMS were mounted onto an electrical Si interposer with through-silicon vias (TSVs) and microfluidic channels. Photonics chips of vertical-cavity surface-emitting lasers and photodiodes were embedded into an optical Si interposer with TSVs. The electrical and optical interposers were precisely bonded together to form a 3-D optoelectronic multichip module. The photonics and electrical devices could communicate via TSVs. The photonics devices could be connected via an optical waveguide formed onto the optical interposer. Microfluidic channels were formed into the interposer by a wafer-direct bonding technique for heat sinking from high-power LSIs. In this paper, we evaluated the basic functions of individual chips of LSI, MEMS, and photonics devices as they were integrated into the 3-D optoelectronic multichip module to verify the applied 3-D hybrid integration technology. LSI, passive, MEMS, and photonics devices were successfully implemented. The 3-D hybrid integration technology is capable of providing a powerful solution for realizing optoelectronic heterogeneous integrated systems.

Takafumi Fukushima

Papers

High-Density Through Silicon Vias for 3-D LSIs

High-Density Through Silicon Vias for 3-D LSIs : Silicon stacked chips that perform highly-parallel data transfer have been successfully fabricated for image processing, artificial retinas, and for microprocessor and memory testing

Three-Dimensional Integration Technology Based on Wafer Bonding With Vertical Buried Interconnections

New three-dimensional integration technology using self-assembly technique

Three-Dimensional Hybrid Integration Technology of CMOS, MEMS, and Photonics Circuits for Optoelectronic Heterogeneous Integrated Systems