F
Franco Fummi
Researcher at University of Verona
Publications - 353
Citations - 3121
Franco Fummi is an academic researcher from University of Verona. The author has contributed to research in topics: SystemC & Automatic test pattern generation. The author has an hindex of 25, co-authored 334 publications receiving 2948 citations. Previous affiliations of Franco Fummi include Telecom Italia & DST Systems.
Papers
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Journal ArticleDOI
SystemC cosimulation and emulation of multiprocessor SoC designs
TL;DR: The authors describe a simulation environment that targets heterogeneous multiprocessor systems and is currently working to extend their methodology to more complex on-chip architectures.
Proceedings ArticleDOI
Implicit test generation for behavioral VHDL models
TL;DR: The paper will experimentally show that the test patterns generated at the behavioral level provide a very high stuck-at fault coverage when applied to different gate-level implementations of the given VHDL behavioral specification.
Proceedings ArticleDOI
A SystemC-based framework for modeling and simulation of networked embedded systems
TL;DR: A modeling language traditionally used for System design -SystemC- is exploited to build a system/network simulator named SystemC Network Simulation Library (SCNSL), which allows to model network scenarios in which different kinds of nodes, or nodes described at different abstraction levels, interact together.
Journal ArticleDOI
HIFsuite: tools for HDL code conversion and manipulation
Nicola Bombieri,Giuseppe Di Guglielmo,Michele Ferrari,Franco Fummi,Graziano Pravadelli,Francesco Stefanni,Alessandro Venturelli +6 more
TL;DR: HIFSuite is a set of tools and application programming interfaces that provide support for modeling and verification of HW/SW systems and allows designers to manipulate and integrate heterogeneous components implemented by using different hardware description languages.
Proceedings ArticleDOI
Native ISS-SystemC integration for the co-simulation of multi-processor SoC
TL;DR: Two co-simulation methodologies are presented, based on SystemC as hardware modeling language and on an instruction set simulator (ISS) as a model of the processor, which improve co-Simulation performance with respect to state-of the art methods and provide different trade-offs between the simplicity of the programming model, the modeling power, and co-SIMulation performance.