The scaling of microchip technologies has enabled large scale systems-on-chip (SoC). Network-on-chip (NoC) research addresses global communication in SoC, involving (i) a move from computation-centric to communication-centric design and (ii) the implementation of scalable communication structures. This survey presents a perspective on existing NoC research. We define the following abstractions: system, network adapter, network, and link to explain and structure the fundamental concepts. First, research relating to the actual network design is reviewed. Then system level design and modeling are discussed. We also evaluate performance analysis techniques. The research shows that NoC constitutes a unification of current trends of intrachip communication rather than an explicit new alternative.

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A survey of research and practices of Network-on-chip

Recent developments and technological advancements in wireless communication, MicroElectroMechanical Systems (MEMS) technology and integrated circuits has enabled low-power, intelligent, miniaturized, invasive/non-invasive micro and nano-technology sensor nodes strategically placed in or around the human body to be used in various applications, such as personal health monitoring. This exciting new area of research is called Wireless Body Area Networks (WBANs) and leverages the emerging IEEE 802.15.6 and IEEE 802.15.4j standards, specifically standardized for medical WBANs. The aim of WBANs is to simplify and improve speed, accuracy, and reliability of communication of sensors/actuators within, on, and in the immediate proximity of a human body. The vast scope of challenges associated with WBANs has led to numerous publications. In this paper, we survey the current state-of-art of WBANs based on the latest standards and publications. Open issues and challenges within each area are also explored as a source of inspiration towards future developments in WBANs.

Wireless Body Area Networks: A Survey

Wireless sensor nodes (WSNs) are employed today in many different application areas, ranging from health and lifestyle to automotive, smart building, predictive maintenance (e.g., of machines and infrastructure), and active RFID tags. Currently these devices have limited lifetimes, however, since they require significant operating power. The typical power requirements of some current portable devices, including a body sensor network, are shown in Figure 1.

Energy Harvesting for Autonomous Wireless Sensor Networks

(1981). Practical Nonparametric Statistics (2nd ed.) Technometrics: Vol. 23, No. 4, pp. 415-416.

Practical Nonparametric Statistics (2nd ed.)

FUNDAMENTALS OF MAGNETIC THEORY Basic Laws of Magnetic Theory Magnetic Materials Magnetic Circuits References FAST DESIGN APPROACH INCLUDING EDDY CURRENT LOSSES Fast Design Approach Examples Conclusions Appendix 2.A.1: Core Size Scale Law for Ferrites in Non-Saturated Thermal Limited Design Appendix 2.A.2: Eddy Current Losses for Wide Frequency Appendix 2.A.3: MathCAD Example Files References SOFT MAGNETIC MATERIALS Magnetic Core Materials Comparison and Applications of the Core Materials in Power Electronics Losses in Soft Magnetic Materials Ferrite Core Losses with Non-Sinusoidal Voltage Waveforms Wide Frequency Model of Magnetic Sheets Including Hysteresis Effects Appendix 3.A: Power and Impedance of Magnetic Sheets References COIL WINDING AND ELECTRICAL INSULATION Filling Factor Wire Length Physical Aspects of Breakdown Insulation Requirements and Standards Thermal Requirements and Standards Magnetic Component Manufacturing Sheet References EDDY CURRENTS IN CONDUCTORS Introduction Basic Approximations Losses in Rectangular Conductors Quadrature of the Circle Method for Round Conductors Losses of a Current Carrying Round Conductor in 2-D Approach Losses of a Round Conductor in a Uniform Transverse AC Field Low Frequency 2-D Approximation Method for Round Conductors Wide Frequency Method for Calculating Eddy Current Losses in Windings Losses in Foil Windings Losses in Planar Windings Appendix 5.A.1: Eddy Current 1-D Model for Rectangular Conductors Appendix 5.A.2: Low Frequency 2-D Models for Eddy Current Losses in Round Wires Appendix 5.A.3: Field Factor For Inductors References THERMAL ASPECTS Fast Thermal Design Approach (Level 0 Thermal Design) Single Thermal Resistance Design Approach (Level 1 Thermal Design) Classic Heat Transfer Mechanisms Thermal Design Utilizing a Resistance Network Contribution to Heat Transfer Theory of Magnetic Components Transient Heat Transfer Summary Appendix 6.A: Accurate Natural Convection Modeling for Magnetic Components References PARASITIC CAPACITANCES IN MAGNETIC COMPONENTS Capacitance Between Windings: Inter Capacitance Self-Capacitance of a Winding: Intra Capacitance Capacitance Between the Windings and the Magnetic Material Practical Approaches for Decreasing the Effects of Parasitic Capacitances References INDUCTOR DESIGN Air Coils and Related Shapes Inductor Shapes Typical Ferrite Inductor Shapes Fringing in Wire-Wound Inductors with Magnetic Cores Eddy Currents in Inductor Windings Foil Wound Inductors Inductor Types Depending on Application Design Examples of Different Types of Inductors Fringing Coefficients For Gapped-Wire-Wound Inductors Analitical Modeling of Combined Litz Wire-Full Wire Inductors References TRANSFORMER DESIGN Transformer Design in Power Electronics Magnetizing Inductance Leakage Inductance Using Parallel Wires and Litz Wires Interleaved Windings Superimposing Frequency Components Superimposing Modes References OPTIMAL COPPER/CORE LOSS RATIO IN MAGNETIC COMPONENTS Simplified Approach Loss Minimization in the General Case Loss Minimization Without Eddy Current Losses Loss Minimization Including Low-Frequency Eddy Current Losses Summary Examples References MEASUREMENTS Introduction Temperature Measurements Power Losses Measurements Measurement of Inductances Core Loss Measurements Measurement of Parasitic Capacitances Combined Measuring Instruments References APPENDIX A: RMS VALUES OF WAVEFORMS Definitions RMS Values of Some Basic Waveforms RMS Values of Common Waveforms APPENDIX B: MAGNETIC CORE DATA ETD Core Data (Economic Transformer Design Core) EE Core Data Planar EE Core Data ER Core Data UU Core Data Ring Core Data (Toroid Core) P Core Data (Pot Core) PQ Core Data RM Core Data APPENDIX C: COPPER WIRES DATA Round Wire Data American Wire Gauge Data Litz Wire Data APPENDIX D: MATHEMATICAL FUNCTIONS References INDEX

Inductors and Transformers for Power Electronics

Spatial Division Multiplexing: a Novel Approach for Guaranteed Throughput

The paper compares two methods for ohmic losses calculation in switch-mode power supply transformers: Dowell's 1D approach and 2D finite element method simulations (validated by measurements). Dowell's method underestimates losses at the fundamental frequency for foil windings, whereas harmonic losses are generally overestimated (depending on conductor type). More significant differences are found with high leakage inductance transformers.

Ohmic losses calculation in SMPS transformers: numerical study of Dowell's approach accuracy

A new formula aimed at calculating ohmic losses in switch-mode power supply (SMPS) transformers is presented. It is based on intensive two-dimensional (2-D) finite element method (FEM) simulations, the results of which have been summarized in a closed-form formula following a "semi-empirical" approach. The main benefit of this new formula, specifically intended for industrial designers, is to combine the precision of 2-D models with the ease-of-use and speed of calculation of one-dimensional (1-D) models, on the whole frequency range. It accurately covers cases where the classical Dowell's formula significantly underestimated the losses, specifically those with significant edge effect in foil windings. Experimental validation and discussion of accuracy is provided. At the moment, the formula is only valid for one layer of foil located between a zero and a maximum of the magnetomotive force but a similar approach could be applied with success to other types of windings. Furthermore, the analytical expression proposed in the article, based on Maxwell equations, can be used as a stand-alone tool to model the real behavior of any type of winding. More accurate understanding of the 2-D field is also possible thanks to the direct link established between the losses and the geometrical data of the winding.

A closed-form formula for 2-D ohmic losses calculation in SMPS transformer foils

To ensure low power consumption while maintaining flexibility and performance, future Systems-on-Chip (SoC) will combine several types of processor cores and data memory units of widely different sizes. To interconnect the IPs of these heterogeneous platforms, Networks-on-Chip (NoC) have been proposed as an efficient and scalable alternative to shared buses. NoCs can provide throughput and latency guarantees by establishing virtual circuits between source and destination. State-of-the-art NoCs currently exploit Time-Division Multiplexing (TDM) to share network resources among virtual circuits, but this typically results in high network area and energy overhead with long circuit set-up time.We propose an alternative solution based on Spatial Division Multiplexing (SDM). This paper describes our first design of an SDM-based network, discusses design alternatives for network implementation and shows why SDM should be better adapted to NoCs than TDM for a limited number of circuits.Our case study clearly illustrates the advantages of our technique over TDM in terms of energy consumption, area overhead, and flexibility. SDM thus deserves to be explored in more depth, and in particular in combination with TDM in a hybrid scheme.

http://cecs.uci.edu/~papers/codes05/PAPERS/2005/CODES_ISSS05/PDFFILES/P081.PDF

Spatial division multiplexing: a novel approach for guaranteed throughput on NoCs

To ensure low power consumption while maintaining flexibility and performance, future systems-on-chip (SoC) will combine several types of processor cores and data memory units of widely different sizes. To interconnect the IPs of these heterogeneous platforms, networks-on-chip (NoC) have been proposed as an efficient and scalable alternative to shared buses. NoCs can provide throughput and latency guarantees by establishing virtual circuits between source and destination. State-of-the-art NoCs currently exploit time-division multiplexing (TDM) to share network resources among virtual circuits, but this typically results in high network area and energy overhead with long circuit set-up time. We propose an alternative solution based on spatial division multiplexing (SDM). This paper describes our design of an SDM-based network, discusses design alternatives for network implementation and shows why SDM can be better adapted to NoCs than TDM in a specific context. Our case study clearly illustrates the advantages of our technique over TDM in terms of energy consumption, area overhead, and flexibility. A comparison is also performed with a state-of-the-art industrial reference NoC: Arteris.

Frédéric Robert

Papers

Spatial Division Multiplexing: a Novel Approach for Guaranteed Throughput

Ohmic losses calculation in SMPS transformers: numerical study of Dowell's approach accuracy

A closed-form formula for 2-D ohmic losses calculation in SMPS transformer foils

Spatial division multiplexing: a novel approach for guaranteed throughput on NoCs

Concepts and Implementation of Spatial Division Multiplexing for Guaranteed Throughput in Networks-on-Chip