To alleviate the complex communication problems that arise as the number of on-chip components increases, network-on-chip (NoC) architectures have been recently proposed to replace global interconnects. In this paper, we first provide a general description of NoC architectures and applications. Then, we enumerate several related research problems organized under five main categories: Application characterization, communication paradigm, communication infrastructure, analysis, and solution evaluation. Motivation, problem description, proposed approaches, and open issues are discussed for each problem from system, microarchitecture, and circuit perspectives. Finally, we address the interactions among these research problems and put the NoC design process into perspective.

Outstanding Research Problems in NoC Design: System, Microarchitecture, and Circuit Perspectives

This paper proposes a solution to the present bulky external capacitor low-dropout (LDO) voltage regulators with an external capacitorless LDO architecture. The large external capacitor used in typical LDOs is removed allowing for greater power system integration for system-on-chip (SoC) applications. A compensation scheme is presented that provides both a fast transient response and full range alternating current (AC) stability from 0- to 50-mA load current even if the output load is as high as 100 pF. The 2.8-V capacitorless LDO voltage regulator with a power supply of 3 V was fabricated in a commercial 0.35-mum CMOS technology, consuming only 65 muA of ground current with a dropout voltage of 200 mV. Experimental results demonstrate that the proposed capacitorless LDO architecture overcomes the typical load transient and ac stability issues encountered in previous architectures.

Full On-Chip CMOS Low-Dropout Voltage Regulator

This paper describes design techniques to maximize the efficiency and power density of fully integrated switched-capacitor (SC) DC-DC converters. Circuit design methods are proposed to enable simplified gate drivers while supporting multiple topologies (and hence output voltages). These methods are verified by a proof-of-concept converter prototype implemented in 0.374 mm2 of a 32 nm SOI process. The 32-phase interleaved converter can be configured into three topologies to support output voltages of 0.5 V-1.2 V from a 2 V input supply, and achieves 79.76% efficiency at an output power density of 0.86 W/mm2 .

Design Techniques for Fully Integrated Switched-Capacitor DC-DC Converters

With the trend towards increasing number of cores in chip multiprocessors, the on-chip interconnect that connects the cores needs to scale efficiently. In this work, we propose the use of high-radix networks in on-chip interconnection net- works and describe how the flattened butterfly topology can be mapped to on-chip networks. By using high-radix routers to reduce the diameter of the network, the flattened butterfly offers lower latency and energy consumption than conven- tional on-chip topologies. In addition, by exploiting the two dimensional planar VLSI layout, the on-chip flattened but- terfly can exploit the bypass channels such that non-minimal routing can be used with minimal impact on latency and en- ergy consumption. We evaluate the flattened butterfly and compare it to alternate on-chip topologies using synthetic traffic patterns and traces and show that the flattened but- terfly can increase throughput by up to 50% compared to a concentrated mesh and reduce latency by 28% while re- ducing the power consumption by 38% compared to a mesh network.

/pdf/flattened-butterfly-topology-for-on-chip-networks-11ww2hm2ph.pdf

Flattened Butterfly Topology for On-Chip Networks

Multicore platforms are emerging trends in the design of System-on-Chips (SoCs). Interconnect fabrics for these multicore SoCs play a crucial role in achieving the target performance. The Network-on-Chip (NoC) paradigm has been proposed as a promising solution for designing the interconnect fabric of multicore SoCs. But the performance requirements of NoC infrastructures in future technology nodes cannot be met by relying only on material innovation with traditional scaling. The continuing demand for low-power and high-speed interconnects with technology scaling necessitates looking beyond the conventional planar metal/dielectric-based interconnect infrastructures. Among different possible alternatives, the on-chip wireless communication network is envisioned as a revolutionary methodology, capable of bringing significant performance gains for multicore SoCs. Wireless NoCs (WiNoCs) can be designed by using miniaturized on-chip antennas as an enabling technology. In this paper, we present design methodologies and technology requirements for scalable WiNoC architectures and evaluate their performance. It is demonstrated that WiNoCs outperform their wired counterparts in terms of network throughput and latency, and that energy dissipation improves by orders of magnitude. The performance of the proposed WiNoC is evaluated in presence of various traffic patterns and also compared with other emerging alternative NoCs.

/pdf/scalable-hybrid-wireless-network-on-chip-architectures-for-5fa4vdmh52.pdf

Scalable Hybrid Wireless Network-on-Chip Architectures for Multicore Systems

Adaptive control of the power supply is one of the most effective variables to achieve energy-efficient computation. In this work, we describe the development of a high-performance asynchronous micropipelined datapath that provides robust interfaces across voltage domains, performing appropriate voltage level conversions and operating between stages with fanout-of-four delays differing by almost two orders of magnitude. With software-specified throughput requirements, the power supply of the datapath is scaled from 2.5 V to 600 mV using an on-chip dc-dc conversion system that combines linear regulators and switched-capacitor power supplies. Because of the asynchronous design style, the processor operates continuously during the voltage scaling transitions.

/pdf/asynchronous-datapath-with-software-controlled-on-chip-4gh969hcz2.pdf

Asynchronous datapath with software-controlled on-chip adaptive voltage scaling for multirate signal processing applications

Adaptive control of the power supply is one of the most effective variables to achieve energy-efficient computation. In this paper, we describe the development of a high-performance asynchronous micropipelined datapath that provides robust interfaces across voltage domains, performing appropriate voltage level conversions and operating between stages with fanout-of-four delays differing by almost two orders of magnitude. With software-specified throughput requirements, the power supply of the datapath is scaled from 2.5 V to 650 mV using an on-chip dc-dc conversion system. Because of the asynchronous design style, the processor operates continuously during the voltage scaling transitions.

High-throughput asynchronous datapath with software-controlled voltage scaling

This paper describes the design of an active CMOS biosensor array for fluorescence-based assays which enables time-gated, time-resolved fluorescence spectroscopy. The array is sensitive to photon densities as low as 1.15 /spl times/ 10/sup 8//cm/sup 2/, has a dynamic range of over 74 dB, and has sub-nanosecond timing resolution. High sensitivity is achieved through subsampling and averaging.

Active CMOS biochip for time-resolved fluorescence detection

It is widely recognized that adaptive control of the power supply is one of the most effective variables to achieve energy-efficient computation. In this work, we describe the development of a high-performance asynchronous micropipelined datapath that provides robust interfaces across voltage domains, performing appropriate voltage level conversions and operating between stages with fanout-of-four delays differing by almost two orders of magnitude. With software-specified throughput requirements, the power supply of the datapath is scaled from 2.5 V to 650 mV using an on-chip dc-dc conversion system that combines linear regulators and switched-capacitor power supplies. Because of the asynchronous design style, the processor operates continuously during the voltage scaling transitions.

https://www.vlsisymposium.org/Past/03web/circuits/cir_pdf/C4p3.pdf

G. Patounakis

Papers

Asynchronous datapath with software-controlled on-chip adaptive voltage scaling for multirate signal processing applications

High-throughput asynchronous datapath with software-controlled voltage scaling

Active CMOS biochip for time-resolved fluorescence detection

High-throughput asynchronous datapath with software-controlled voltage scaling

How to deal with confounders in an infertility study?