An electrically erasable programmable read only memory (EEPROM) having a non conducting charge trapping dielectric, such as silicon nitride, sandwiched between two silicon dioxide layers acting as electrical insulators is disclosed. The invention includes a method of programming, reading and erasing the EEPROM device. The non conducting dielectric layer functions as an electrical charge trapping medium. A conducting gate layer is placed over the upper silicon dioxide layer. The memory device is programmed in the conventional manner, using hot electron programming, by applying programming voltages to the gate and the drain while the source is grounded. Hot electrons are accelerated sufficiently to be injected into the region of the trapping dielectric layer near the drain. The device, however, is read in the opposite direction from which it was written, meaning voltages are applied to the gate and the source while the drain is grounded. Application of relatively low gate voltages combined with reading in the reverse direction greatly reduces the potential across the trapped charge region. This permits much shorter programming times by amplifying the effect of the charge trapped in the localized trapping region. In addition, the memory cell can be erased by applying suitable erase voltages to the gate and the drain so as to cause electrons to be removed from the charge trapping region of the nitride layer. Similar to programming, a narrower charge trapping region enables much faster erase cycles.

Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping

A high k dielectric film and methods for forming the same are disclosed. The high k material includes two peaks of impurity concentration, particularly nitrogen, such as at a lower interface and upper interface, making the layer particularly suitable for transistor gate dielectric applications. The methods of formation include low temperature processes, particularly CVD using a remote plasma generator and atomic layer deposition using selective incorporation of nitrogen in the cyclic process. Advantageously, nitrogen levels are tailored during the deposition process and temperatures are low enough to avoid interdiffusion and allow maintenance of the desired impurity profile.

Incorporation of nitrogen into high k dielectric film

A memory cell array has a first and a second storage area. The first storage area has a memory elements selected by an address signal. The second storage area has a memory elements selected by a control signal. A control circuit has a fuse element. When the fuse element has been blown, the control circuit inhibits at least one of writing and erasing from being done on the second storage area.

Nonvolatile Semiconductor Memory Device

Non-volatile memory cells store a level of charge corresponding to the data being stored in a dielectric material storage element that is sandwiched between a control gate and the semiconductor substrate surface over channel regions of the memory cells. More than two memory states are provided by one of more than two levels of charge being stored in a common region of the dielectric material. More than one such common region may be included in each cell. In one form, two such regions are provided adjacent source and drain diffusions in a cell that also includes a select transistor positioned between them. In another form, NAND arrays of strings of memory cells store charge in regions of a dielectric layer sandwiched between word lines and the semiconductor substrate.

Multi-state non-volatile integrated circuit memory systems that employ dielectric storage elements

The present invention presents a hybrid non-volatile system that uses non-volatile memories based on two or more different non-volatile memory technologies in order to exploit the relative advantages of each these technology with respect to the others. In an exemplary embodiment, the memory system includes a controller and a flash memory, where the controller has a non-volatile RAM based on an alternate technology such as FeRAM. The flash memory is used for the storage of user data and the non-volatile RAM in the controller is used for system control data used by the control to manage the storage of host data in the flash memory. The use of an alternate non-volatile memory technology in the controller allows for a non-volatile copy of the most recent control data to be accessed more quickly as it can be updated on a bit by bit basis. In another exemplary embodiment, the alternate non-volatile memory is used as a cache where data can safely be staged prior to its being written to the to the memory or read back to the host.

Hybrid non-volatile memory system

A non-volatile storage cell comprising a field effect transistor having source, gate, and drain electrodes. The gate electrode includes a gate stack having a dielectric layer, a charge storage structure comprising a layer of silicon-rich silicon nitride having sufficient excess silicon to provide appreciable charge storage enhancement, without providing appreciable charge conductance enhancement, as compared to stoichiometric silicon nitride, and a charge injection means. A control electrode is disposed on the gate stack for effecting charge transfer to and from the silicon-rich silicon nitride layer through the charge injection means. An array of these cells is formed by disposing the FETs within independently biased substrate portions. Thus the cells can be overwritten without an intervening erasure cycle.

Non-volatile memory cell having Si rich silicon nitride charge trapping layer

A circuit card unit comprising a memory card and attached heat exchanger comprising a thin, flexible, laminated strip of foil clad plastic, or wire mesh, affixed in thermally conductive contact to each card module and extended therefrom to facilitate removal of heat from the modules. In some embodiments, the exchanger strip extends from the modules on one side of the card to those of the other side in a self supporting, heat exchanger loop spaced over the memory card. In a somewhat more compact embodiment, the strip extends from modules on one card face, along the card itself, to the modules of the other card face. In a still further embodiment, the heat exchanger strip extends from the modules of the card to a heat sink such as the housing of the computer. Additionally, the heat exchanger strips may also function as a carrier for an identifying label printed on, or attached to, the planar surface of the strip.

Integrated heat exchanger for memory module

At-speed test of integrated circuits is becoming critical to detect subtle delay defects. Existing structural at-speed test methods are inadequate because they are unable to supply sufficiently-varied functional clock sequences to test complex sequential logic. Moreover, they require tight restrictions on the circuit design. In this paper, we present a new method for at-speed structural test of ASICs, having no tight restrictions on the circuit design. In the present implementation, any complex at-speed functional clock waveform for 16 cycles can be applied. We present DFT structures that can generate high-speed launch-off-capture as well as launch-off-scan clocking without the need to switch a scan enable at-speed. We also describe a method to test asynchronous clock domains simultaneously. Experimental results on fault coverage and hardware measurements for three multi-million gate ASICs demonstrate the feasibility of the proposed approach.

At-Speed Structural Test For High-Performance ASICs

A scanner using a small, inexpensive CCD array for accurately and easily re-creating an error free reproduction of any scanned image wherein a plurality of laser alignment marks are temporarily projected, from an inexpensive solid state laser via a low cost plastic fiber optic cable, onto the surface of the document, and capturing the image as a number of small segments, along both the horizontal and vertical dimensions of the document onto the surface of the image being scanned. These temporary, projected, alignment marks permit the accurate positioning of adjacent, scanned segments during reconstruction of the scanned document. This scanner can scan documents of any width with an accuracy such that the scanned document can be readily, easily and accurately reassembled regardless of the insensitivity of, or misalignment of the scanning array in the apparatus or the skew of the document relative to the camera doing the scanning.

Non-destructive target marking for image stitching

A system for enhancing the practicability of at-speed structural testing (ASST). In one embodiment, the system includes first means for performing statistical timing analysis on a design of logic circuitry. A second means performs a criticality analysis on the logic circuitry as a function of the statistical timing analysis so as to determine a criticality probability for each node of the logic circuitry. A third means selects nodes of the logic circuitry as a function of the criticality analysis. A fourth means selects timing paths as a function of the criticality probabilities of the selected nodes. A fifth means generates an ASST pattern for each of the selected timing paths. A sixth mean is provided to perform ASST on a fabricated instantiation of the design at functional speed using the generated ASST pattern.

Gary D. Grise

Papers

Non-volatile memory cell having Si rich silicon nitride charge trapping layer

Integrated heat exchanger for memory module

At-Speed Structural Test For High-Performance ASICs

Non-destructive target marking for image stitching

System and method for generating at-speed structural tests to improve process and environmental parameter space coverage