In this paper, a summary of published techniques for power conditioning within energy harvesting systems is presented. The focus is on low-power systems, e.g, <;10 mW, for kinetic energy harvesting. Published concepts are grouped according to functionality and results contrasted. The various techniques described are considered in terms of complexity, efficiency, quiescent power consumption, startup behavior, and utilization of the harvester compared to an optimum load. This paper concludes with an overview of power management techniques that aim to maximize the extracted power and the utilization of the energy harvester.

Review of Power Conditioning for Kinetic Energy Harvesting Systems

We present an active full-wave rectifier with offset-controlled high speed comparators in standard CMOS that provides high power conversion efficiency (PCE) in high frequency (HF) range for inductively powered devices. This rectifier provides much lower dropout voltage and far better PCE compared to the passive on-chip or off-chip rectifiers. The built-in offset-control functions in the comparators compensate for both turn-on and turn-off delays in the main rectifying switches, thus maximizing the forward current delivered to the load and minimizing the back current to improve the PCE. We have fabricated this active rectifier in a 0.5-μm 3M2P standard CMOS process, occupying 0.18 mm2 of chip area. With 3.8 V peak ac input at 13.56 MHz, the rectifier provides 3.12 V dc output to a 500 Ω load, resulting in the PCE of 80.2%, which is the highest measured at this frequency. In addition, overvoltage protection (OVP) as safety measure and built-in back telemetry capabilities have been incorporated in our design using detuning and load shift keying (LSK) techniques, respectively, and tested.

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An Integrated Power-Efficient Active Rectifier With Offset-Controlled High Speed Comparators for Inductively Powered Applications

We present an inductively powered 32-channel wireless integrated neural recording (WINeR) system-on-a-chip (SoC) to be ultimately used for one or more small freely behaving animals. The inductive powering is intended to relieve the animals from carrying bulky batteries used in other wireless systems, and enables long recording sessions. The WINeR system uses time-division multiplexing along with a novel power scheduling method that reduces the current in unused low-noise amplifiers (LNAs) to cut the total SoC power consumption. In addition, an on-chip high-efficiency active rectifier with optimized coils help improve the overall system power efficiency, which is controlled in a closed loop to supply stable power to the WINeR regardless of the coil displacements. The WINeR SoC has been implemented in a 0.5-μ m standard complementary metal-oxide semiconductor process, measuring 4.9×3.3 mm2 and consuming 5.85 mW at ±1.5 V when 12 out of 32 LNAs are active at any time by power scheduling. Measured input-referred noise for the entire system, including the receiver located at 1.2 m, is 4.95 μVrms in the 1 Hz~10 kHz range when the system is inductively powered with 7-cm separation between aligned coils.

An inductively powered scalable 32-channel wireless neural recording system-on-a-chip for neuroscience applications

A power-efficient wireless stimulating system for a head-mounted deep brain stimulator (DBS) is presented. A new adaptive rectifier generates a variable DC supply voltage from a constant AC power carrier utilizing phase control feedback, while achieving high AC-DC power conversion efficiency (PCE) through active synchronous switching. A current-controlled stimulator adopts closed-loop supply control to automatically adjust the stimulation compliance voltage by detecting stimulation site potentials through a voltage readout channel, and improve the stimulation efficiency. The stimulator also utilizes closed-loop active charge balancing to maintain the residual charge at each site within a safe limit, while receiving the stimulation parameters wirelessly from the amplitude-shift-keyed power carrier. A 4-ch wireless stimulating system prototype was fabricated in a 0.5-μm 3M2P standard CMOS process, occupying 2.25 mm2. With 5 V peak AC input at 2 MHz, the adaptive rectifier provides an adjustable DC output between 2.5 V and 4.6 V at 2.8 mA loading, resulting in measured PCE of 72 ~ 87%. The adaptive supply control increases the stimulation efficiency up to 30% higher than a fixed supply voltage to 58 ~ 68%. The prototype wireless stimulating system was verified in vitro.

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A Power-Efficient Wireless System With Adaptive Supply Control for Deep Brain Stimulation

This brief presents a standalone closed-loop wireless power transmission system that is built around a commercial off-the-shelf (COTS) radio-frequency identification (RFID) reader (TRF7960) operating at 13.56 MHz. It can be used for inductively powering implantable biomedical devices in a closed loop. Any changes in the distance and misalignment between transmitter and receiver coils in near-field wireless power transmission can cause a significant change in the received power, which can cause either a malfunction or excessive heat dissipation. RFID circuits are often used in an open loop. However, their back telemetry capability can be utilized to stabilize the received voltage on the implant. Our measurements showed that the delivered power to the transponder was maintained at 11.2 mW over a range of 0.5 to 2 cm, while the transmitter power consumption changed from 78 mW to 1.1 W. The closed-loop system can also oppose voltage variations as a result of sudden changes in the load current.

/pdf/an-rfid-based-closed-loop-wireless-power-transmission-system-3nn9jcdq1h.pdf

An RFID-Based Closed-Loop Wireless Power Transmission System for Biomedical Applications

In this paper, we present an active rectifier with high power conversion efficiency (PCE) implemented in a 0.5- mum 5 V standard CMOS technology with two modes of built-in back telemetry; short- and open-circuit. As a rectifier, it ensures a PCE > 80%, taking advantage of active synchronous rectification technique in the frequency range of 0.125-1 MHz. The built-in complementary back telemetry feature can be utilized in implantable microelectronic devices (IMD), wireless sensors, and radio frequency identification (RFID) applications to reduce the silicon area, increase the data rate, and improve the reading range and robustness in load shift keying (LSK).

Active High Power Conversion Efficiency Rectifier With Built-In Dual-Mode Back Telemetry in Standard CMOS Technology

In this paper we present analysis, design, and implementation of a high-efficiency active full-wave rectifier in standard CMOS technology. The rectifier takes advantage of the dynamic voltage control of its separated n-well regions, where the main rectifying PMOS elements have been implemented in order to eliminate latch-up and body effect. To minimize rectifier dropout and improve AC---DC power conversion efficiency (PCE), all the MOSFET switching elements have been pushed into deep triode region to minimize their resistance along the main current path during conduction. A prototype rectifier was implemented in the AMI 0.5-μm 3M/2P n-well CMOS process. An input sinusoid of 5 V peak at 0.5 MHz produced 4.36 V DC output across a $$1\,\hbox{k}\Upomega\Vert 1\,\mu\hbox{F}$$ load, resulting in a measured PCE of 84.8%.

Analysis, design, and implementation of a high-efficiency full-wave rectifier in standard CMOS technology

In this paper, a high efficiency full-wave integrated voltage rectifier, implemented in AMI 0.5-mum 3M/2P n-well standard CMOS process, is presented. The rectifier takes advantage of the dynamic voltage control of separated n-well regions, where the main rectifying PMOS elements have been implemented, to eliminate latchup and body effect. In measurements, an AC input sinusoid of 5 V peak at 0.5 MHz yield a 4.36 V DC output across a 1 kOmega load, resulting in a measured power conversion efficiency of 85%.

A high efficiency full-wave rectifier in standard CMOS Technology

A system, DC-DC converter, and compensation method and circuit for a DC-DC converter are disclosed. For example, a compensation circuit for a DC-DC converter is disclosed. The compensation circuit includes an integrator circuit configured to receive and integrate a first voltage signal, a differential difference amplifier circuit coupled to the integrator circuit and configured to generate a first filter transfer function associated with the integrated first voltage signal, and a switched capacitor filter circuit coupled to the differential difference amplifier circuit and configured to generate a second filter transfer function, wherein the differential difference amplifier is further configured to output a second voltage signal responsive to the first filter transfer function and the second filter transfer function. In one implementation, the compensation circuit is a type-III switched capacitor filter (SCF) compensation circuit.

Enhanced switched capacitor filter (scf) compensation in dc-dc converters

In this paper, we present an active rectifier with high power conversion efficiency (PCE) implemented in a 0.5- mum 5 V standard CMOS process with two modes of built-in back telemetry; short- and open-circuit. As a rectifier, it ensures a PCE > 80%, taking advantage of active synchronous rectification technique in the frequency range of 0.125 - 1 MHz. The built-in complementary back telemetry feature in this rectifier can be utilized in implantable microelectronic devices, radio frequency identification (RFID), and wireless sensor applications to reduce the silicon area, improve the reading range, and increase the data rate with load shift keying (LSK).

Gaurav Bawa

Papers

Active High Power Conversion Efficiency Rectifier With Built-In Dual-Mode Back Telemetry in Standard CMOS Technology

Analysis, design, and implementation of a high-efficiency full-wave rectifier in standard CMOS technology

A high efficiency full-wave rectifier in standard CMOS Technology

Enhanced switched capacitor filter (scf) compensation in dc-dc converters

A back telemetry-capable active high efficiency rectifier in standard CMOS process