Showing papers in "Analog Integrated Circuits and Signal Processing in 2009"

Novel voltage/current-mode quadrature oscillator using current differencing transconductance amplifier

Abstract: This letter proposes a new realization of voltage/ current-mode (CM) quadrature oscillator (QO) using Current Differencing Transconductance Amplifier (CDTA) as the active element. The proposed circuit employs canonic number of components, namely two CDTAs, one resistor and two grounded capacitors. The oscillator is capable of providing two explicit quadrature current outputs and two quadrature voltage outputs. Moreover, the circuit enjoys the advantage of independent control of condition of oscillation (CO) and frequency of oscillation (FO). The non-ideal analysis and sensitivity study of the circuit has been carried out and the circuit exhibits a good sensitivity performance. B2SPICE simulation results are included that validate the working of the circuit.

CMOS-based near zero-offset multiple inputs max---min circuits and its applications

Abstract: CMOS-based near zero-offset multiple inputs maximum circuit and minimum circuits are proposed. The analog signal building blocks including shunt-feedback buffer, voltage-subtraction circuits and current mirrors are deployed for obtained the good performances. This achieved circuit is a simply scheme and able to work with low-power supplies. The input range is obtained around ±600 mV within ±1.5 V power supplies. Near zero-offset and low-output impedance are provided by proposed circuit. The delay of output is less than 5 ns for THD less than 1% and frequency response up to 500 MHz. Half-wave, full-wave rectifiers and 4 bits linear combination Digital-to-Analog Converter (DAC) are raised up to confirm the realistic applications. All performances including the DC-characteristic, frequency response, high-frequency wave output are simulated by PSpice.

Tunable mixed-mode OTA-C universal filter

Abstract: A novel electronically tunable mixed-mode universal biquad by using four single-output and one dual-output-operational transconductance amplifiers, two grounded capacitors is proposed. The proposed circuit has ability to realize voltage, current, transconductance, and transresistance mode, and can the following advantageous features: (i) realization of low-pass, band-pass, high-pass, notch, and all-pass filter responses from the same configuration, (ii) employment of only grounded capacitors ideal for integrated circuit implementation, (iii) orthogonal controlling of ? o and Q for easily electronic tunability, and (iv) low active and passive sensitivity performance. Finally, to verify our architecture, we have designed this analog filter chip with TSMC 0.35-μm 2P4M CMOS technology. This chip operates to 1 MHz and consumes 30.95 mW. The chip area of the analog filter is about 0.823 mm2.

Novel lossless and lossy grounded inductor simulators consisting of a canonical number of components

Abstract: In this paper, four series lossy inductor simulators including a minimum number of active and passive components, a current feedback operational amplifier (CFOA), two resistors and a capacitor, are proposed. Also, four lossless simulated inductors using a canonical number of elements, a new CFOA, two resistors and a capacitor, are developed. All the introduced circuits do not need critical component matching constraints. Simulations achieved by means of SPICE program are added so as to demonstrate the performance.

The VCG-CCII: a novel building block and its application to capacitance multiplication

Abstract: A new current mode building block named voltage and current gain second generation current conveyor (VCG-CCII) is introduced. The voltage and current buffers of the standard CCII are replaced by voltage and current amplifiers with tunable gains so to obtain an extremely flexible and versatile building block. The VCG-CCII can be used in place of the standard CCII in impedance conversion applications so to utilize only one active component. A circuit implementation in a standard 0.35 μm CMOS process is presented and used to multiply, as an example, a 10 pF capacitor by a factor tunable from 1 up to about 3100, achieving a capacitance multiplication for more than 6 decades frequency range (from 0.15 to 865 KHz for the highest multiplication factor).

Cascadable allpass filter with a single DO-CCII and a grounded capacitor

Abstract: In the literature sufficient emphasis has not been given to dual-output current conveyors in all-pass filter designs. In this study, a cascadable voltage-mode all-pass filter with a grounded capacitor using a single dual-output current conveyor has been reported.

ICCII-based universal current-mode analog filter employing only grounded passive components

Abstract: In this paper, three versions of a novel second-order current-mode (CM) single-input three-output analog filter employing inverting second-generation current conveyors (ICCIIs) and only grounded passive components, are presented. This filter can simultaneously realize low-pass, band-pass and high-pass responses, and can also realize notch and all-pass filter responses with interconnection of the relevant output currents. The presented second-order filter requires no active and passive element matching conditions and/or cancellation constraints. The proposed filter offers orthogonal control of angular resonance frequency (?o) and quality factor (Q). The proposed filter can realize filter responses at high output impedances, and has low active and passive component sensitivities. Additionally, three versions of a high-order filter derived from the proposed filter are introduced. Simulation results using SPICE program are given to show the performance of the filter and verify the theory. Signal limitations and non-ideal current and voltage gain effects of the proposed second-order filter are also investigated.

Discussion on the general oscillation startup condition and the Barkhausen criterion

Abstract: The Barkhausen criterion has been widely used to determine the oscillation startup condition. However, we propose it is only partially correct. The general oscillation condition and the relation between the general oscillation condition and the Barkhausen criterion are reviewed in this paper. The oscillation frequency related to the general oscillation startup condition is also presented.

A new electronically tunable current mode universal filter using MO-CCCII

Abstract: A new electronically tunable universal current mode biquad filter structure employing three multiple output current controlled conveyors (MOCCCII) and two grounded capacitors is presented. The proposed filter offers the following advantageous features: low input impedance and high output impedance--a desirable property of current mode filters; realization of low pass, band pass, high pass, notch, and all pass; no matching constraint; low sensitivity performance and use of grounded capacitors suitable for integration. The practical design problems due to nonlinearities of MOCCCIIs have also been addressed. The feasibility of the design is confirmed via SPICE simulations.

Analysis, design, and implementation of a high-efficiency full-wave rectifier in standard CMOS technology

Abstract: In this paper we present analysis, design, and implementation of a high-efficiency active full-wave rectifier in standard CMOS technology. The rectifier takes advantage of the dynamic voltage control of its separated n-well regions, where the main rectifying PMOS elements have been implemented in order to eliminate latch-up and body effect. To minimize rectifier dropout and improve AC---DC power conversion efficiency (PCE), all the MOSFET switching elements have been pushed into deep triode region to minimize their resistance along the main current path during conduction. A prototype rectifier was implemented in the AMI 0.5-μm 3M/2P n-well CMOS process. An input sinusoid of 5 V peak at 0.5 MHz produced 4.36 V DC output across a $$1\,\hbox{k}\Upomega\Vert 1\,\mu\hbox{F}$$ load, resulting in a measured PCE of 84.8%.

A 6.4 mW, 4.9 nV/√Hz, 24 dBm IIP3 VGA for a multi-standard (WLAN, UMTS, and Bluetooth) receiver

Abstract: A low-power high-linearity variable-gain-amplifier (VGA) to be embedded in a multi-standard receiver (WLAN, UMTS and Bluetooth) is reported. The multi-standard receiver architecture presents considerable different VGA requirements (in terms of bandwidth, DC-gain, noise level, and common mode input voltage) for the three telecom standards. The VGA is positioned just after the mixer, and, then, it operates on low- amplitude input signals. This results in stronger noise requirements than linearity ones. Thus a digitally controlled open-loop structure has been used. The prototype VGA is realized in a 0.13 μm CMOS technology and it features gain levels from -10 to 36 dB. For 0 dB DC-gain it exhibits a 25 dBm IIP3 and an input-referred noise voltage lower than 5 nV/√Hz. This gives a 85 dB-DR for the WLAN case. The VGA draws 6.4 mA from a single 2.5 V supply.

A 0.5 V bulk-input OTA with improved common-mode feedback for low-frequency filtering applications

Abstract: This paper presents the design of a two-stage pseudo-differential operational transconductance amplifier (OTA) and its application in low-frequency continuous time filters. The OTA was designed in a 0.18 μm, 0.45 V V T CMOS process. An improved bulk-mode common-mode feedback (CMFB) circuit has been designed which does not load the OTA compared to prior art. A self cascode load structure and partial positive feedback provide higher gain. The bulk terminals of all transistors have been biased to lower their threshold voltages (VT) and maximize signal swing. The OTA operates at a supply voltage of 0.5 V and consumes only 28 μW of power. Rail-to-rail input is made possible by using the transistor's bulk terminal as the input. For a load of 20 pF the OTA has a measured DC gain of 63 dB and a gain-bandwidth product of 570 kHz. To demonstrate the use of the OTA in practical circuits, three active RC filters were designed: a 10 kHz Butterworth filter, a 10 kHz Bessel filter, and a 2.5 kHz Tschebycheff filter.

CMOS based capacitive sensor laboratory-on-chip: a multidisciplinary approach

Abstract: In this paper, we review the recent advances of CMOS-based capacitive sensors for Lab-on-chip (LoC) applications. LoC design is a multidisciplinary approach of adapting classical biochemical assays to a miniaturized platform by exploiting advances in microelectronic and microfluidic technologies. By offering low cost and integrated devices, CMOS based LoCs could be amenable to a large number of biological and biochemical assays for disease diagnostics and biotechnology in the near future. While an exhaustive, all-encompassing review of CMOS-based LoCs is beyond the scope of this review, we have focused on the design and implementation of CMOS-based capacitive sensor LoCs for the most important biochemical applications. For each application, the corresponding biochemical sensing layer, interface circuit and microfluidic packaging technique are discussed based on the recent literature studies.

Multi-function biquad using single current differencing transconductance amplifier

Abstract: An universal multi input single output type multifunction biquad is proposed. The proposed configuration employs only one current differencing transconductance amplifier as the active element, two capacitors and three resistors. The circuit realizes all five filter functions (i.e. Low Pass, High Pass, Band Pass, Notch and All Pass) without changing the circuit topology. The natural frequency ?0 is independently and electronically tunable. The workability of the proposed multifunction biquad has been verified using SPICE simulation.

Scaling prospect of optically differential reconfigurable gate array VLSIs

Abstract: Dynamic reconfigurable devices present new computational paradigms because programmable devices' activity and performance can be improved dramatically by increasing its reconfiguration frequency. Therefore, this paper presents designs of optically differential reconfigurable gate array (ODRGA) VLSIs using 0.18 μm and 0.35 μm CMOS process technologies. Although they are a type of programmable gate array, they can be reconfigured optically in nanoseconds. This paper also discusses future scaling prospects of ODRGA-VLSIs.

Design strategies for multi-channel low-noise recording systems

Abstract: Parallel recording of micro-scale signals using an integrated system approach has become feasible with recent advances in technology. Practical applications include the recording of neural-signals in a brain-computer interface or in prosthetic implants. In an integrated circuit implementation the restriction in size and available power pose considerable challenges, especially in implanted devices. Furthermore, the provision of both high gain and excellent noise performance in the presence of input offset voltages are mandatory. The presented tutorial highlights design strategies for recording system optimization and compares the performance of actual system implementations with the best-case performance achievable in theory. Special consideration is given to the noise vs. power and offset-tolerance vs. noise trade-offs. An application dependent design strategy is proposed.

A novel heuristic for multi-objective optimization of analog circuit performances

Abstract: We present a novel heuristic for optimizing analog circuit performances. It deals with generating the Pareto front using the topological properties of the feasible solution space. This heuristic allows us generating optimal values of circuit parameters in reduced computation time and memory consumption. Unlike basic metaheuristics, it does not need optimization background from the user in order to be easily adapted to different applications. It can thus be smoothly integrated into an automated design flow. This novel approach enables us to further improve (good) performances that were already reached using other optimizing techniques. Robustness of the algorithm was proved using specific difficult test problems.

Analytical model-based technique for efficient evaluation of noise robustness considering parameter variations

Abstract: In this paper, we present an accurate method for analytical derivation of noise rejection curves (NRCs) and the associated noise susceptibility metric in the presence of variations in process and environmental parameters. The method involves modeling of the pull-up and pull-down resistances of combinational gates using approximated BSIM4 model-based device equations. Comparisons of the analytical model with circuit simulations show that the impact of parameter variations on the noise susceptibility is accurately captured by our model. The average (maximum) error associated with the noise susceptibility is found to be as low as 2.6% (6.7%). Our model can predict the noise susceptibility under parameter variations more than five orders of magnitude faster than circuit simulations, which makes it suitable for design optimization for noise robustness.

Novel high-precision current-mode multiplier/divider

Abstract: In this paper, a method to reduce the second order effects on the circuit performances caused by the small sized MOS transistors is proposed. A current mode square-root circuit, a squarer/divider circuit and a multiplier/divider circuit are designed using this method. Proposed circuits have been simulated with SPICE simulator using 0.35 μm CMOS technology parameters. The main advantages of the proposed circuit are reduced errors of the output current function, a smaller area on the chip, possibility of controlling the output current with the control voltage, operation at higher frequencies and more efficient power consumption. As a result, it can be considered as a useful building block for IC designer.

Wavelet-based hybrid ECG compression technique

Abstract: In this paper, a new wavelet-based hybrid electrocardiogram (ECG) data compression technique is proposed. Firstly, in order to fully utilize the two correlations of heartbeat signals, 1-D ECG data are segmented and aligned to a 2-D data arrays. Secondly, 2-D wavelet transform is applied to the constructed 2-D data array. Thirdly, the set partitioning hierarchical trees (SPIHT) method and the vector quantization (VQ) method are modified, according to the individual characteristic of different coefficient subband and the similarity between the subbands. Finally, a hybrid compression method of the modified SPIHT and VQ is employed to the wavelet coefficients. Records selected from the MIT/BIH arrhythmia database are tested. The experimental results show that the proposed method is suitable for various morphologies of ECG data, and that it achieves high compression ratio with the characteristic features well preserved.

New low component count floating inductor simulators consisting of a single DDCC

Abstract: In this paper, five novel and minimum number count floating inductor simulators (FIs) are proposed Three of the presented FIs depending on the passive component choice can provide parallel R---L, (---R)---(---L) and series R---L, (---R)---(---L) from the same configuration while other two provide one of parallel R---L or series R---L Some of the introduced positive lossy inductor simulators employ a grounded capacitor; accordingly, they are convenient for integrated circuit (IC) implementation So as to exhibit the performance of the proposed structures, computer simulations based on SPICE program are given

Low voltage current mirrors with enhanced bandwidth

Abstract: This paper presents an improved low voltage cascode and flipped voltage follower (FVF) based current mirror with the enhancement of the bandwidth obtained by using a compensation resistor between the gates of the primary transistor pair. In this technique a carefully determined resistance is used in the diode connected MOS transistor of the current mirror for enhancing the bandwidth. Active realization of the compensation resistance using MOS operating in the triode region has also been applied to both the cascode and FVF based current mirror circuits. The proposed circuits have been simulated using PSpice for 0.25 μm CMOS technology and the obtained results are compared with their uncompensated topologies to show their effectiveness.

Very high-speed and high-accuracy current-steering CMOS D/A converter using a novel 3-D decoder

Abstract: In this paper a 10-bit 1.2-GSample/s Nyquist current-steering CMOS digital-to-analog converter (DAC) is presented. Segmentation (90%) has been used to get the best DNL and reduce glitch energy. This segmentation ratio guarantees the monotonicity. Higher performance is achieved using a novel 3-D thermometer decoding method which reduces the area, power consumption, and the number of control signals of the digital section. Simulation results show that the spurious-free-dynamic-range (SFDR) in Nyquist rate is better than 65 dB for sampling frequency up to 1.2-GSample/s. The analog voltage supply is 3.3 V while the digital part of the chip operates at only 2.4 V. Total power consumption in Nyquist rate measurement is 149 mW. The chip has been processed in a standard 0.35 μm CMOS technology. Active area of chip is 1.97 mm2.

An ultra-low power ISM-band integer-N frequency synthesizer dedicated to implantable medical microsystems

Abstract: In this article, the architectural choices and design of a fully integrated integer-N frequency synthesizer operating in the 902---928 MHz Industrial, Scientific and Medical (ISM) band is presented. This frequency synthesizer, optimized for ultra-low power operation, is being integrated in the transceiver of an implantable wireless sensing microsystem (IWSM), which is dedicated to in vivo monitoring of biological parameters such as temperature, pressure, pH, oxygen, and nitric oxide concentrations. This phase-locked loop-based synthesizer includes a 1.830 GHz LC voltage-controlled oscillator (VCO) using a 10 nH on chip inductor. Varactors are implemented using P+ in N-well diodes for their linearity and high quality factor. The transistors of the VCO are operated in moderate inversion, and their bias point was chosen using the g m/I d design methodology. The output of the VCO, operating at twice the ISM frequency band, is divided by 2 to generate differential, quadrature versions of the carrier. Power minimization of the programmable divider was achieved by designing the latches and flip-flops using appropriate circuit techniques such as True Single Phase Clocking (TSPC) and first-type Dynamic Single Transistor Clocking (DSTC1) depending on their operating frequency. The power consumption of the proposed synthesizer is 580 μW under 1 V; almost an order of magnitude lower compared to that of recent synthesizer designs having a similar architecture.

Design and analysis of a CMOS passive ΣΔ ADC for low power RF transceivers

Abstract: Design and analysis of a ΣΔ modulator with a passive switched capacitor loop filter is presented. Design steps for optimum loop filter design for quantization noise suppression and thermal noise reduction is outlined. Design specifications for sampling clock phase noise, reference buffer and input buffer settling is analyzed. Presented design has a 2nd-order loop filter and uses only metal-metal capacitors and thin oxide digital transistors with no additional components occupying less than 0.1 mm2 silicon area in 0.13 µm CMOS digital process. Measurement results show that the ADC achieves 80 dB peak SNR at a 100 kHz integration bandwidth with 1 pJ/sample conversion efficiency. With decimation filter power consumption of 0.22 mW at 104 MHz sampling rate, the ADC consumes only about 1 mA at 1.5 V for each channel.

Simulation of a novel current-mode universal filter using FDCCIIs

Abstract: In this paper, a new current-mode universal active-RC filter is proposed. The proposed circuit is based on a new universal passive filter topology. This passive filter is generated from a classical well known current-mode universal passive filter applying a transformation procedure. Two Fully Differential Current Conveyors (FDCCII) are used to construct a universal active-RC filter from this passive filter. The FDCCII based proposed filter has only grounded resistors and capacitors as the passive elements. The circuit simultaneously provides the three basic filter characteristics, namely high-pass (HP), band-pass (BP) and low-pass (LP). SPICE simulation results are given to verify the theoretical analysis.

Extended frequency-band-decomposition sigma---delta A/D converter

Abstract: Parallelism can be used to increase the bandwidths of ADC converters based on sigma---delta modulators. Each modulator converts a part of the input signal band and is followed by a digital filter. Unfortunately, solutions using bandpass sigma---delta modulators are very sensitive to the position of the modulators' central frequencies. This paper shows the feasibility of a frequency-band-decomposition (FBD) ADC using continuous time bandpass sigma---delta modulators, even in the case of large analog mismatches. The major benefit of such a solution, called extended-frequency-band-decomposition (EFBD) is its low sensitivity to analog parameters. For example, a relative error in the central frequencies of 4% can be accepted without significant degradation in the performance (other published FBD ADCs require a precision of the central frequencies better than 0.1%). This paper will focus on the performance which can be reached with this system, and the architecture of the digital part. The quantization of coefficients and operators will be addressed. It will be shown that a 14 bit resolution can be theoretically reached using 10 sixth-order bandpass modulators at a sampling frequency of 800 MHz which results in a bandwidth of 80 MHz centered around 200 MHz (the resolution depends on the effective quality factor of the filters of the analog modulators).

Trade-offs in the OTA-based analog filter design

Abstract: Operational transconductance amplifiers (OTAs) are widely used in the design of electronically tunable circuits. However, electronic tunability ranges of the OTA based filters are restricted by the limited bandwidth of the transconductance gain of the OTA. Furthermore, stability conditions and the linearity of the OTA which depends on the control current restrict the tunability. In this paper, some trade-offs in the electronically tunable filters are investigated. In addition, the tunability ranges of some first and second order OTA-C and OTA-RC filters are comparatively examined. Moreover, an OTA-C all-pass filter circuit is presented. SPICE simulations are performed and stability analyses are given for both of the OTA-C and OTA-RC filters. Operation of the presented all-pass filter is verified experimentally.

Mechanical fatigue analysis of gold microbeams for RF-MEMS applications by pull-in voltage monitoring

Abstract: This work is focused on the reliability of gold microcantilevers under the effect of mechanical fatigue. A dedicated device for testing the material is designed and built; the material degradation is monitored during the tests by means of a novel technique based on the control of the pull-in voltage of the device, which was demonstrated to be related to the loss of mechanical strength. The fatigue effect is produced through the excitation of the device at a frequency near the resonance; the excitation frequency and the time of actuation are used as a counter for the number of cycles. The lifetime of the device is measured under variable levels of vibration amplitudes; the number of cycles to failure is estimated within a specific range of actuation voltages by means of the Wohler diagram obtained by experiments. The fatigue limit is also estimated following the stair-case method.

Current-controlled current differencing transconductance amplifier and applications in continuous-time signal processing circuits

Abstract: This article presents the design for a basic current-mode building block for analogue signal processing, named as Current Controlled Current Differencing Transconductance Amplifier (CCCDTA) Its parasitic resistances at two current input ports can be controlled by an input bias current As it can be applied in current-mode of all terminals, it is very suitable to use in a current-mode signal processing, which is continually more popular than a voltage one The proposed element is realized in a bipolar technology and its performance is examined through PSPICE simulations They display usability of the new active element, where the maximum bandwidth is 65 MHz The CCCDTA performs low-power consumption and tuning over a wide current range In addition, some examples as a current-mode universal biquad filter, a current-mode multiplier/divider and floating inductance simulator are included They occupy only single CCCDTA