Showing papers by "Gordon W. Roberts published in 2016"

A Jitter Injection Signal Generation and Extraction System for Embedded Test of High-Speed Data I/O

Abstract: An instrument for on-chip measurement of transceiver transmission capability is described that is fully realizable in CMOS technology and embeddable within an SoC. The instrument can be used to inject and extract the timing and voltage information associated with signals in high-speed transceiver circuits that are commonly found in data communication applications. At the core of this work is the use of ΣΔ amplitude- and phase-encoding techniques to generate both the voltage and timing (phase) references, or strobes used for high-speed sampling. The same technique is also used for generating the test stimulant for the device-under-test.

Synthesis of High Gain Operational Transconductance Amplifiers for Closed-Loop Operation Using a Generalized Controller-Based Compensation Method

Abstract: This paper presents a systematic procedure that can be used to create operational transconductance amplifiers (OTAs) for closed-loop operation using multiple low-gain stages to realize extremely high DC gain. Such devices are necessary to realize analog functions with demanding absolute accuracy requirements, e.g., high-resolution ADCs and DACs. The principle is based on the cascade of undamped integrators to realize large DC gains and a state-space derived controller to stabilize its operation in a closed-loop configuration. A programmable OTA fabricated in the IBM 130 nm CMOS process is used as a test vehicle to prove the design principle through its 2 to 5th-order realization. Measured data reveals DC gains ranging from 50 to 150 dB with a 3-dB bandwidth of 10 kHz and a unity gain frequency of 10 MHz. While this paper demonstrates the design principles using CMOS integrated circuits, the principle is general and can be applied to any type of circuit technology in integrated or discrete implementation. Moreover, the methods are easily automated as the principles are based on closed-form formulae as opposed to iterative numerical search techniques.

Low-cost trimmable manufacturing methods for printable electronics

Abstract: While printable electronics (PE) has the potential to provide a low cost means to manufacture electronic solutions, it suffers serious levels of component variations. While many of the problems facing PE are early technological development yield-related problems, some are more fundamental to its manufacturing nature. In this work, methods to construct PE circuits that compensate for these variations will be described. These methods include a combination of printing, severing, and ink deposition techniques that are performed both during and after manufacturing. Data obtained from working prototypes made using the PE technology at the National Research Council (NRC) of Canada will be described.

Mixed-signal ATE technology and its impact on today's electronic system

Abstract: Analog/Mixed-Signal test is usually thought of as a quality control step in the manufacture of electronic devices — largely to separate good devices from bad. In this paper, the case is made that analog/mixed-signal semiconductor test technology has been at the forefront of many of today's analog SOC design approaches. This is most likely quite opposite to what most engineers think about test. The reason is quite simple — analog test engineers are concerned with a multitude of design issues that span across many different engineering domains such as mechanical, electrical, electronic, firmware and software. Moreover, they have always been pressed to achieve accurate measurements in near minimum time. As a result, analog test engineers have always had their eye on the big picture and created test solutions decades ago that would rival any analog system platform today. This paper will take a look to the past and see how test technology has impacted present-day system approaches such as those used in data communications, general purpose analog signal processing, etc.

A Top–Down Design Methodology Encompassing Components Variations Due to Wide-Range Operation in Frequency Synthesizer PLLs

Abstract: This paper presents a complete methodology to model, design, and implement wide tuning-range phase-locked loops (PLLs) using a top–down approach. Mathematical equations that illustrate the contribution of the different sources of noise in the PLL are presented. Behavioral models that encompass the nonidealities of the PLL components are described using Verilog-A language. The PLL components are designed, and the noise performance of each component is evaluated using transistor-level simulations. The extracted jitter from the individual blocks is used to find the overall system noise. The proposed methodology considers the variations in the loop dynamics due to changes in the voltage-controlled oscillator gain and noise, frequency divider ratio, and charge pump current. While optimizing the PLL for maximum tuning range, the methodology also considers the tradeoff between the noise, speed, and reference spurs attenuation. The design and implementation of an integer- $N$ frequency synthesizer PLL that covers a continuous frequency range from 156.25 MHz to 10 GHz using a 65-nm CMOS technology is demonstrated in this paper. Measurement results to verify the accuracy of the models and to validate the predictions made by the simulations are provided.

Experimental operation of time-mode building blocks using a time-mode switched-delay unit

Abstract: This paper provides experimental verification of the functionality of some existing basic time-mode signal processing (TMSP) building blocks having an all-digital advantage. Experimental data that covers all necessary aspects of operation such as transfer functions, linearity and frequency response is presented. Simulations are compared to measured data and performance limitations are introduced such as the hard linearity limit imposed by the switched-delay unit discharge time. In addition, some of these building blocks were used to design a second-order filter for the first time demonstrating a peak SNDR value of 45.5 dB making it a good candidate for data conversion applications.

Design of high-order type-II delay-locked loops using a Gaussian transfer function approach

Abstract: In this article, a method of designing high-order DLLs is presented and verified through both simulations and physical experiments. The general approach is based on selecting the transfer function of the closed-loop DLL and deriving the loop filter behavior based on the gain of the phase-detector and voltage-controlled delay line. The proposed approach does not rely on the principle of design based on achieving a desired phase margin specifications but rather is based on selecting a closed-loop DLL behavior based on a desired Gaussian transfer function. Experimental results are provided to support the claims.

Top-down design and synthesis of inherently-stable integrator-based high-order amplifiers

Abstract: A defined, straightforward top-down design method is proposed for developing inherently-stable, fast-settling high-order amplifiers. The method effectively defines the closed-loop response for a multistage amplifier through a desirable transfer function, such as of a time-domain filter, and combines an efficient g m -based procedure to implement a compact corresponding CMOS circuit. The amplifier will be composed of a cascade of g m -C integrators to supply the dc gain, followed by a stabilizing controller. Hence, several gain stages, more than the typical three, can be employed to build high-order structures that can achieve ultra-high gain. In support of the proposed approach, a four-stage operational transconductance amplifier (OTA) with a third-order modified-Bessel unity-gain feedback response is implemented in 0.13-µm CMOS. Simulation results demonstrate that the OTA achieves a dc gain of 78 dB and realizes the anticipated, pre-defined closed-loop response while driving a 1-pF capacitive load.

A digitally programmable 50–150dB DC gain operational transconductance amplifier in 130nm CMOS

Abstract: This paper presents an operational transconductance amplifier for closed-loop operation with extremely high DC gain and large gain-bandwidth product. The design principle is based on the cascade of undamped integrators to realize large DC gains and a controller to stabilize its operation in a closed-loop configuration. With a predetermined set of numbers, the OTA can be programmed into different states to realize various transfer functions and system orders. Gaussian transfer function is implemented as an example in this work. The chip is fabricated in the IBM 130 nm CMOS process, and measured data reveals DC gains ranging from 50 to 150 dB with a minimum 3-dB bandwidth of 10 kHz and a unity gain frequency of 10 MHz. This design principle is general and can be applied to any type of circuit technology in integrated or discrete implementation.