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Design Of Analog Cmos Integrated Circuits

A simple high-performance architecture for bulk-driven operational transconductance amplifiers (OTAs) is presented. The solution, suitable for operation under sub 1-V single supply, is made up of three gain stages and, as an additional feature, provides inherent class-AB behavior with accurate and robust standby current control. The OTA is fabricated in a 180-nm standard CMOS technology, occupies an area of $19.8\cdot 10^{-3}\ \text{mm}^{2}$ and is powered from 0.7 V with a standby current consumption of around 36 $\mu\text{A}$ . DC gain and unity gain frequency are 57 dB and 3 MHz, respectively, under a capacitive load of 20 pF. Overall good large-signal and small-signal performances are achieved, making the solution extremely competitive in comparison to the state of the art.

0.7-V Three-Stage Class-AB CMOS Operational Transconductance Amplifier

Design and implementation of sub 0.5‐V OTAs in 0.18‐μm CMOS

In this article, a new solution for an ultralow-voltage (ULV) ultralow-power (ULP) operational transconductance amplifier (OTA) is presented. Thanks to the combination of a low-voltage bulk-driven nontailed differential stage with the multipath Miller zero compensation technique, a simple class AB power-efficient ULV structure has been obtained, which can operate from supply voltages less than the threshold voltages of the employed MOS transistors, while offering rail-to-rail input common-mode range at the same time. The proposed OTA was fabricated using the 180-nm CMOS process from Taiwan Semiconductor Manufacturing Company (TSMC) and can operate from $V_{\mathbf {DD}}$ ranging from 0.3 to 0.5 V. The 0.3-V version dissipates only 12.6 nW of power while showing a 64.7-dB voltage gain at 1-Hz, 2.96-kHz gain-bandwidth product, and a 4.15-V/ms average slew-rate at 30-pF load capacitance. The measured results agree well with simulations.

A Compact 0.3-V Class AB Bulk-Driven OTA

This paper introduces a new effective single-Miller capacitor compensation topology for three-stage amplifiers with very large capacitive loads, realized through an active-feedback capacitor together with an inner half-feedforward stage. Moreover, an optimized design strategy which profitably exploits the two left half-plane zeros is presented. To improve the amplifier large signal transient response, the topology also includes an external feedforward path, that only marginally affects the frequency compensation, and a novel slew-rate enhancer section. To validate the solutions presented, a three-stage OTA driving a 10-nF load has been designed and implemented in a standard 0.35- $\mu\text{m}$ CMOS technology. The amplifier occupies less than 0.003-mm2 of die area, provides 2.7-MHz gain-bandwidth product and 0.55-V/ $\mu\text{s}$ average slew-rate, while consuming only 25- $\mu\text{A}$ quiescent current.

Optimized Active Single-Miller Capacitor Compensation With Inner Half-Feedforward Stage for Very High-Load Three-Stage OTAs

An operational-transconductance-amplifier (OTA) design for ultra-low voltage ultra-low power applications is proposed. The input stage of the proposed OTA utilizes a bulk-driven pseudo-differential pair to allow minimum supply voltage while achieving a rail-to-rail input range. All the transistors in the proposed OTA operate in the subthreshold region. Using a novel self-biasing technique to bias the OTA obviates the need for extra biasing circuitry and enhances the performance of the OTA. The proposed technique ensures the OTA robustness to process variations and increases design feasibility under ultra-low-voltage conditions. Moreover, the proposed biasing technique significantly improves the common-mode and power-supply rejection of the OTA. To further enhance the bandwidth and allow the use of smaller compensation capacitors, a compensation network based on a damping-factor control circuit is exploited. The OTA is fabricated in a 65 nm CMOS technology. Measurement results show that the OTA provides a low-frequency gain of 46 dB and rail-to-rail input common-mode range with a supply voltage as low as 0.5 V. The dc gain of the OTA is greater than 42 dB for supply voltage as low as 0.35 V. The power dissipation is 182 $\mu{\rm W}$ at $V_{DD}=0.5\ {\rm V}$ and 17 $\mu{\rm W}$ at $V_{DD}=0.35\ {\rm V}$ .

An Ultra-Low-Voltage CMOS Process-Insensitive Self-Biased OTA With Rail-to-Rail Input Range

An operational-transconductance-amplifier (OTA) design for low-voltage low-power applications is proposed. The proposed OTA incorporates bulk-driven MOS transistors in the pseudo differential pair of the input stage to concurrently enable low voltage operation and rail-to-rail input range. Using a common-mode feedforward (CMFF) circuit in the first stage to bias the following stages of the OTA obviates the need for extra biasing circuitry and improves the performance of the OTA. To further enhance the bandwidth and allow the use of smaller compensation capacitors, a compensation network based on a damping factor control circuit is exploited. To verify the theoretical findings, the OTA was fabricated in a 65 nm CMOS technology. Measurements show that the OTA provides a low-frequency gain of 46 dB at Vdd = 0.5 V, and a gain of 43 dB at Vdd = 0.35 V. The power dissipation is 182 μW at Vdd = 0.5 V, and 17 μW at Vdd = 0.35 V.

A 0.35-V bulk-driven self-biased OTA with rail-to-rail input range in 65 nm CMOS

A bandgap voltage reference that operates from a power supply of 0.6 V is presented in this paper. The circuit is based on an all-CMOS implementation that allows operation below the base-emitter voltage limit by eliminating parasitic vertical bipolar-junction-transistors. Low-voltage design techniques are deployed to design an op-amp that can obviate the need for a start-up circuit. The design was implemented in 65 nm CMOS technology. The measured reference voltage is 275 mV with an average temperature coefficient of 176 ppm/°C from −50°C to 80°C without trimming. The circuit consumes 62 μW of power and occupies 0.011 mm2 of chip area.

A 0.6V-supply bandgap reference in 65 nm CMOS

This paper presents a complete methodology to model, design, and implement wide tuning-range phase-locked loops (PLLs) using a top–down approach. Mathematical equations that illustrate the contribution of the different sources of noise in the PLL are presented. Behavioral models that encompass the nonidealities of the PLL components are described using Verilog-A language. The PLL components are designed, and the noise performance of each component is evaluated using transistor-level simulations. The extracted jitter from the individual blocks is used to find the overall system noise. The proposed methodology considers the variations in the loop dynamics due to changes in the voltage-controlled oscillator gain and noise, frequency divider ratio, and charge pump current. While optimizing the PLL for maximum tuning range, the methodology also considers the tradeoff between the noise, speed, and reference spurs attenuation. The design and implementation of an integer- $N$ frequency synthesizer PLL that covers a continuous frequency range from 156.25 MHz to 10 GHz using a 65-nm CMOS technology is demonstrated in this paper. Measurement results to verify the accuracy of the models and to validate the predictions made by the simulations are provided.

A Top–Down Design Methodology Encompassing Components Variations Due to Wide-Range Operation in Frequency Synthesizer PLLs

This paper presents the main challenges in the design of wide tuning range LC voltage controlled oscillators (LC-VCOs) in CMOS technologies. Design trade-offs such as tank losses, phase noise, and power consumption are discussed and analyzed. A VCO that has a wide tuning range that covers frequencies from 5.5 GHz to 10.2 GHz was designed and fabricated in a 65 nm CMOS process. The worst case measured phase noise is -83 dBc/Hz at 1 MHz frequency offset from the carrier. The design occupies 0.125 mm 2 silicon area, and dissipates 11 mW (excluding the buffers).

Yi-Chi Shih

Papers

An Ultra-Low-Voltage CMOS Process-Insensitive Self-Biased OTA With Rail-to-Rail Input Range

A 0.35-V bulk-driven self-biased OTA with rail-to-rail input range in 65 nm CMOS

A 0.6V-supply bandgap reference in 65 nm CMOS

A Top–Down Design Methodology Encompassing Components Variations Due to Wide-Range Operation in Frequency Synthesizer PLLs

Optimization of LC-VCO tuning range under different inductor/varactor losses limitations