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Proceedings ArticleDOI

Exploring sub-20nm FinFET design with predictive technology models

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TLDR
Predictive MOSFET models are critical for early stage design-technology co-optimization and circuit design research and PTM for FinFET devices are generated for 5 technology nodes corresponding to the years 2012-2020 on the ITRS roadmap.
Abstract
Predictive MOSFET models are critical for early stage design-technology co-optimization and circuit design research In this work, Predictive Technology Model files for sub-20nm multi-gate transistors have been developed (PTM-MG) Based on MOSFET scaling theory, the 2011 ITRS roadmap and early stage silicon data from published results, PTM for FinFET devices are generated for 5 technology nodes corresponding to the years 2012-2020 on the ITRS roadmap

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Citations
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Journal ArticleDOI

Benchmarking of Beyond-CMOS Exploratory Devices for Logic Integrated Circuits

TL;DR: In this paper, a benchmarking of beyond-CMOS exploratory devices for logic integrated circuits is presented, which includes new devices with ferroelectric, straintronic, and orbitronic computational state variables.
Journal ArticleDOI

Scaling equations for the accurate prediction of CMOS device performance from 180 nm to 7 nm

TL;DR: This work curve fit second and third-order polynomials to circuit delay, energy, and power dissipation results based on HSpice simulations utilizing the Predictive Technology Model (PTM) and International Technology Roadmap for Semiconductors (ITRS) models.
Proceedings ArticleDOI

Open Cell Library in 15nm FreePDK Technology

TL;DR: The proposed cell library is intended to provide access to advanced technology node for universities and other research institutions, in order to design digital integrated circuits and also to develop cell-based design flows, EDA tools and associated algorithms.
Journal ArticleDOI

Current-Induced Spin-Orbit Torques for Spintronic Applications.

TL;DR: Recent advances in SOT research are reviewed, highlighting the considerable benefits and challenges of SOT-based spintronic devices, and major experimental results for field-free SOT switching of perpendicular magnetization are summarized.
Journal ArticleDOI

Complementary logic operation based on electric-field controlled spin-orbit torques

TL;DR: In this paper, the critical current for spin-orbit-torque-induced switching of perpendicular magnetization can be efficiently modulated by an electric field via the voltage-controlled magnetic anisotropy effect.
References
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Proceedings ArticleDOI

New paradigm of predictive MOSFET and interconnect modeling for early circuit simulation

TL;DR: A new paradigm of predictive MOSFET and interconnect modeling is introduced to specifically address SPICE compatible parameters for future technology generations and comparisons with published data and 2D simulations are used to verify this predictive technology model.
Journal ArticleDOI

Comparison of Junctionless and Conventional Trigate Transistors With $L_{g}$ Down to 26 nm

TL;DR: In this paper, the authors presented the first experimental comparison of short-channel JAM-to-IM devices at matched off-state leakage (Ioff) and showed that the JAM devices showed better channel mobility and lower gate capacitance than the IM control counterparts at matched Ioff.
Proceedings ArticleDOI

Tri-Gate Transistor Architecture with High-k Gate Dielectrics, Metal Gates and Strain Engineering

TL;DR: In this paper, the benefits of the fully depleted tri-gate transistor architecture with high-k gate dielectrics, metal gate electrodes and strain engineering are combined with high performance NMOS and PMOS trigate transistors.
Journal ArticleDOI

A process-tolerant cache architecture for improved yield in nanoscale technologies

TL;DR: This technique dynamically detects and replaces faulty cells by dynamically resizing the cache and surpasses all the contemporary fault tolerant schemes such as row/column redundancy and error-correcting code (ECC) in handling failures due to process variation.
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