Spectroscopic ellipsometry was used to investigate the oxidation of pure Hf films on silicon for the formation of HfO2 (hafnium oxide) gate-dielectric films in advanced complementary metal-oxide-semiconductor field-effect transistors Absorption coefficients near the absorption edge were extracted using the data inversion method, in which the optical constants for short wavelengths were calculated using the film thickness determined from long-wavelength data The extracted optical band gap of 57 eV matches well with published data, and a curve shift due to crystallization was detected In addition, an extra absorption peak corresponding to electron transition from the valence band to a defect energy level was observed in the range 45–50 eV above the valence-band edge The 12 eV energy difference between the conduction-band edge and the edge of this extra peak is close to the electron trap energy level reported elsewhere The intensity of the detected peak was clearly correlated with leakage current an

Observation of bulk HfO2 defects by spectroscopic ellipsometry

With the advent of novel device structures that can be easily fabricated outside of the traditional (100) plane, it may be advantageous to change the crystal orientation to optimize CMOS circuit performance. The use of alternative surface orientations such as [110] and (111) enhances hole mobility while degrading electron mobility, thus allowing for adjustment of the ratio between nMOS and pMOS transistor drive currents. By optimizing the surface orientation, up to a 15% improvement in gate delay can be expected. This value depends upon the type of logic gate, the off-state leakage specification, and technology scaling trends. The introduction of high-/spl kappa/ dielectrics may provide an added incentive for the use of non-(100) orientations as this method of circuit performance enhancement may be used to compensate for mobility degradation from the high-/spl kappa/ interface. Additional concerns including layout area and device reliability are discussed.

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CMOS circuit performance enhancement by surface orientation optimization

High-frequency (HF) modeling of MOSFETs for radio-frequency (RF) integrated circuit (IC) design is discussed Modeling of the intrinsic device and the extrinsic components is discussed by accounting for important physical effects at both dc and HF The concepts of equivalent circuits representing both intrinsic and extrinsic components in a MOSFET are analyzed to obtain a physics-based RF model The procedures of the HF model parameter extraction are also developed A subcircuit RF model based on the discussed approaches can be developed with good model accuracy Further, noise modeling is discussed by analyzing the theoretical and experimental results in HF noise modeling Analytical calculation of the noise sources has been discussed to understand the noise characteristics, including induced gate noise The distortion behavior of MOSFET and modeling are also discussed The fact that a MOSFET has much higher "low-frequency limit" is useful for designers and modelers to validate the distortion of a MOSFET model for RF application An RF model could well predict the distortion behavior of MOSFETs if it can accurately describe both dc and ac small-signal characteristics with proper parameter extraction

MOSFET modeling for RF IC design

Preface. MOSFET Device Physics and Operation. MOSFET Fabrication. RF Modeling. Noise Modeling. Proper Modeling for Accurate Distortion Analysis. The BSIM4 MOSFET Model. The EKV Model. Other MOSFET Models. Bipolar Transistors in CMOS Technologies. Modeling of Passive Devices. Effects and Modeling of Process Variation and Device Mismatch. Quality Assurance of MOSFET Models. Index.

Device Modeling for Analog and RF CMOS Circuit Design: Ytterdal/Device

As the gate oxide thickness decreases below 2 nm, the gate leakage current increases dramatically due to direct tunneling current. This large gate leakage current will be an obstacle to reducing gate oxide thickness for the high speed operation of future devices. A MOS transistor with Ta/sub 2/O/sub 5/ gate dielectric is fabricated and characterized as a possible replacement for MOS transistors with ultra-thin gate silicon dioxide. Mobility, I/sub d/-V/sub d/, I/sub d/-V/sub g/, gate leakage current, and capacitance-voltage (C-V) characteristics of Ta/sub 2/O/sub 5/ transistors are evaluated and compared with SiO/sub 2/ transistors. The gate leakage current is three to five orders smaller for Ta/sub 2/O/sub 5/ transistors than SiO/sub 2/ transistors.

Transistor characteristics with Ta/sub 2/O/sub 5/ gate dielectric

The widely accepted universal dependence of N- and P-MOSFETs carrier mobility on effective vertical field E eff = (ηQ inv + Q b ) ϵ Si has been re-examined. New empirical mobility models for both electrons and holes expressed in terms of Tox, Vt and Vg explicitly are formulated. New empirical mobility models are confirmed with experimental data taken from devices of different technologies. It is also shown that the hole mobility of both the surface and buried channel P-MOSFETs can be unified for the first time by a single universal mobility equation, rather than two separate equations as previously thought necessary.

Mosfet carrier mobility model based on gate oxide thickness, threshold and gate voltages

https://ir.nctu.edu.tw:443/bitstream/11536/134760/1/1ce2aaa8eb4e02aa09f3795b7d8cc97b.pdf

H. Clement Wann

Papers

Mosfet carrier mobility model based on gate oxide thickness, threshold and gate voltages

Nearly Dislocation-free Ge/Si Heterostructures by Using Nanoscale Epitaxial Growth Method