Jaeger's buffer comprises a string of tapered inverters. Each inverter is molded by a capacitor and a conductor. In this work, the capacitor is split into inherent and load components (C/sub x/ and C/sub y/), and it is shown that the value of the optimal taper depends on the C/sub x//C/sub y/ ratio: the best taper exceeds Jaeger's 2.72 slope, but only moderately. >

CMOS tapered buffer

Presents an an assessment of new field-effect transistor, resonant tunnel device, single-electron transistor and quantum cellular automata technologies. The goal of this article is to provide technical assessments of new logic technologies. We attempt to "cast a broad net" to gather in one place alternative concepts for logic that would, if successful, substantially extend the International Technology Roadmap for Semiconductors (ITRS) beyond CMOS. The discussions provide some detail regarding device operation principles, advantages, challenges, maturity, and current and projected performance. The scaling of CMOS device and process technology, as it is known today, is projected to continue (7-nm physical channel length) by 2019. The grand challenge, then, is to invent and develop one or more new technologies that will extend the scaling of information-processing technologies through multiple generations beyond 2019. Such new technologies must meet certain fundamental requirements and possess certain compelling attributes to justify the very substantial investments that are necessary to build a new infrastructure.

Emerging research logic devices

The influence of different MOS and bipolar device parameters on the switching speed of a BiCMOS buffer is described. This influence is studied by looking at the response of a BiCMOS inverter to a step input. Using suitable approximations for the high-level injection effects in the bipolar transistor, mathematical approximations for the response are derived. The approximate responses are compared to those determined by SPICE simulations and the agreement is satisfactory. High-current effects in the bipolar transistor strongly affect the performance. The effects of different bipolar transistor parasitic resistors are investigated, and it is found that only the collector resistance is important. The influence of different emitter sizes on the delay time is studied, and it is shown that for a given area, there is one optimal size ratio for the MOS and bipolar transistors for which the delay is minimum. >

Influence of device parameters on the switching speed of BiCMOS buffers

We report the fabrication and characterization of nanowire electromechanical switches consisting of chemical-vapour-deposition-grown silicon nanowires suspended over metal electrodes. The devices operate as transistors with the suspended part of the nanowire bent to touch metal electrodes via electromechanical force by applying voltage. The reversible switching, large on/off current ratio, small subthreshold slope and low switching energy compared to current CMOSFET make the switches very attractive for logic device application. In addition, we have developed a physical model to investigate the switching characteristics and extract the material properties.

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Silicon nanowire electromechanical switches for logic device application

How overshoot in the step response of a circuit involving an RLC line can be controlled using a combination of driver and line resistance that depends on the load capacitance is shown. The no-peak condition or its equivalent is used to relate line parameters to the driver and load impedances. This no-peak condition generalizes the impedance matching customarily used for lossless lines, i.e. it provides an alternative to the traditional choice R/sub D/= square root L/C. The results allow improved circuit response without risk of overshoot, for example, by reduction of driver resistance below square root L/C for cases where line resistance is unavoidable and/or where load capacitance is not negligible compared to line capacitance. The algebraic formulas derived are more effective than case-by-case numerical simulations for analyzing scaling and technology issues, whether on-chip, or at the packaging, board, or system levels. >

Overshoot-controlled RLC interconnections

In this paper, rules are presented for the optimized design of CMOS-bipolar drivers for large capacitive loads typical of VLSI interconnects. Simulations and closed-form solutions show that the n-p-n bipolar transistors have to be operated in the high-level injection mode, and that their sizes have to be tailored to the two-thirds power of the load, and it scales with the two-thirds power of the base width of the n-p-n transistor and with the one-third power of the channel length of the MOS transistor. For comparison, the CMOS cascade with a tailored second stage is shown to have competitive potential at the expense of an area being approximately 2.5 times larger than that of a CMOS-bipolar stage.

Optimization and scaling of CMOS-bipolar drivers for VLSI interconnects

The integration of InAs/AlSb/GaSb resonant interband tunneling diodes (RITDs) with InAlAs/InGaAs/InP high electron mobility transistors (HEMTs) is reported. The integrated devices exhibit nearly identical performance to discrete control devices from DC through microwave frequencies. RITDs with peak current densities of 24.5 kA/cm/sup 2/ and peak voltages of 0.12 V have been demonstrated for devices with 1.2-nm thick AlSb barriers. HEMTs with 0.2-/spl mu/m gates have been fabricated, and f/sub t/s of 127 GHz and f/sub max/ of 183 GHz have been obtained. To the authors' knowledge, this is the first report of the monolithic integration of RITDs with HEMTs on InP.

Fabrication of monolithically-integrated InAlAs/InGaAs/InP HEMTs and InAs/AlSb/GaSb resonant interband tunneling diodes

The development of a semi-empirical model that predicts the electron mobility in silicon as a function of the electric field in the

Field-dependent electron mobility in silicon between 8 and 77 K-a semi-empirical model

We report for the first time the monolithic integration of high-speed submicron gate length InAlAs-InGaAs-InP HEMTs with InAs-AlSb-GaSb resonant interband tunneling diodes (RITDs) for ultra-high-speed IC applications. The epitaxial layers for the integrated RITD/HEMT device process were deposited by molecular beam epitaxy (MBE) on 2" semi-insulating InP substrates. Critical aspects of MBE growth process development include: (1) nucleation of a smooth, strain-relaxed InAs n/sup +/ buffer layer on top of the InGaAs-InAlAs HEMT device layers to provide a growth template and bottom contact for the InAs-AlSb-GaSb RITD active layers, and (2) two AlAs etch stop layers to allow uniform removal of the RITD layers for HEMT processing and uniform gate recess etching. In situ substrate temperature control using an absorption edge spectroscopy sensor was used to nucleate the strain-relaxed InAs buffer at a substrate temperature of 400/spl deg/C followed by heating to 480/spl deg/C for growth of a 150 nm buffer layer. A smooth, thin buffer layer is advantageous for integration of the RITD and HEMT devices in that the RITD device mesas can be short (0.4 /spl mu/m), yielding a relatively planar process geometry. A 50 nm-thick lattice-matched InGaAs layer was deposited between the RITD/HEMT isolation AlAs etch stop layer and the strain-relaxed InAs buffer layer to ensure the structural integrity of the etch stop layer. A carrier concentration of 2.7 10/sup 12/ cm/sup -2/ and mobility of 9500 cm/sup 2//Vs in the HEMT channel were measured. These values are comparable to a control HEMT-only heterostructure.

H.J. de los Santos

Papers

Optimization and scaling of CMOS-bipolar drivers for VLSI interconnects

Fabrication of monolithically-integrated InAlAs/InGaAs/InP HEMTs and InAs/AlSb/GaSb resonant interband tunneling diodes

Field-dependent electron mobility in silicon between 8 and 77 K-a semi-empirical model

Monolithic integration of InAlAs-InGaAs-InP HEMTs and InAs-AlSb-GaSb resonant interband tunneling diodes (RITDs) for high speed integrated circuits