In principle, the exponential of a matrix could be computed in many ways. Methods involving approximation theory, differential equations, the matrix eigenvalues, and the matrix characteristic polyn...

/pdf/nineteen-dubious-ways-to-compute-the-exponential-of-a-matrix-49qnou6xyl.pdf

Nineteen Dubious Ways to Compute the Exponential of a Matrix, Twenty-Five Years Later ⁄

/pdf/nineteen-dubious-ways-to-compute-the-exponential-of-a-matrix-10fp740cmm.pdf

Nineteen Dubious Ways to Compute the Exponential of a Matrix

The Waveform Relaxation (WR) method is an iterative method for analyzing nonlinear dynamical systems in the time domain. The method, at each iteration, decomposes the system into several dynamical subsystems each of which is analyzed for the entire given time interval. Sufficient conditions for convergence of the WR method are proposed and examples in MOS digital integrated circuits are given to show that these conditions are very mild in practice. Theoretical and computational studies show the method to be efficient and reliable.

The Waveform Relaxation Method for Time-Domain Analysis of Large Scale Integrated Circuits

The paper examines states in the gap in amorphous silicon and chalcogenides and their effect on photoconductivity, luminescence and drift mobility. It is supposed that carriers in an ‘ideal’ glassy semiconductor without defects would move by hopping at the band edge at low temperatures and by excitation to a mobility edge at high temperatures, and that the carriers do not form polarons; the results of Spear and co-workers (e.g. Spear 1974 a) for glow-discharge-deposited silicon and of Nagels, Callearts and Denayer (1974) for quenched As2Te3 containing silicon are considered. The effectively zero value of the Hall coefficient in the hopping regime is discussed. States in the gap are supposed to be due to dangling bonds which may form pairs at divacancies; if the concentration is high, these may have a predominating effect on the conductivity and in this case polaron-type hopping could occur, both for chalcogenides and for silicon. For the chalcogenides (in contrast to silicon), it is proposed, ada...

States in the gap and recombination in amorphous semiconductors

The biomimetic CMOS dynamic vision and image sensor described in this paper is based on a QVGA (304×240) array of fully autonomous pixels containing event-based change detection and pulse-width-modulation (PWM) imaging circuitry. Exposure measurements are initiated and carried out locally by the individual pixel that has detected a change of brightness in its field-of-view. Pixels do not rely on external timing signals and independently and asynchronously request access to an (asynchronous arbitrated) output channel when they have new grayscale values to communicate. Pixels that are not stimulated visually do not produce output. The visual information acquired from the scene, temporal contrast and grayscale data, are communicated in the form of asynchronous address-events (AER), with the grayscale values being encoded in inter-event intervals. The pixel-autonomous and massively parallel operation ideally results in lossless video compression through complete temporal redundancy suppression at the pixel level. Compression factors depend on scene activity and peak at ~1000 for static scenes. Due to the time-based encoding of the illumination information, very high dynamic range - intra-scene DR of 143 dB static and 125 dB at 30 fps equivalent temporal resolution - is achieved. A novel time-domain correlated double sampling (TCDS) method yields array FPN of 56 dB (9.3 bit) for >10 Lx illuminance.

A QVGA 143 dB Dynamic Range Frame-Free PWM Image Sensor With Lossless Pixel-Level Video Compression and Time-Domain CDS

We present in this paper a compact model of bipolar transistors, suitable for network analysis computer programs. Through the use of a new charge control relation linking junction voltages, collector current, and base charge, the model includes high injection effects. The performance substantially exceeds that of existing models of comparable complexity. For low bias and with some additional idealization, the model reduces to the conventional Ebers-Moll model.

An integral charge control model of bipolar transistors

A new circuit simulator is described which combines the gate-to-gate signal propagation technique used in logic simulators with detailed device representation and circuit analysis at the gate level. MOTIS is specialized for analyses of MOS logic circuits during the prelayout and postlayout phases of a design. The device modeling takes account of the back-gate bias effects and the bidirectionality of transmission gates. The simulation mechanism and the detailed device modeling lead to simulation of the dependence of propagation delays on input waveforms. The loading and device capacitances are assumed to be constant and bootstrapping effects are not simulated. The simulator has been implemented on a minicomputer having a 32K-word memory of 16-bit words, a disk module, and a storage CRT/keyboard terminal. This configuration allows simulation of circuits having 1000 gates with an operational speed of approximately 2 ms of real time per gate per nanosecond of circuit time.

MOTIS-An MOS timing simulator

The classical capacitance-voltage relations based on abrupt space-charge edge approximations, while adequate at large reverse bias, do not adequately describe the capacitance near zero bias. This paper presents explicit capacitance-voltage relations valid near zero bias for linearly graded and exponential-constant profiles. For linearly graded junctions, the intercept in a 1/C3versus voltage plot is shown to be well approximated by the "gradient voltage" defined by V g = 2/3 kT/q ln a2ekT/q/8qn i 3. Also presented is an accurate numerical technique for machine computation of the transition region capacitance for any doping profile. Explicit relations obtained by dimensional considerations and curve fitting on numerical solutions are free of singularities, hence useful in computer-aided device design and doping profile determination.

Transition region capacitance of diffused p-n junctions

Thermal capture of electrons in silicon

A numerical technique is presented for calculating the resistance of two-terminal distributed resistors and the resistance matrix for multiterminal regions in integrated circuit layers. The technique, useful for computer-aided design of multiterminal resistors, makes use of Cauchy's integral formula which facilitates coordination of conformal transformations at Singular boundary points. Results for a simple test structure (16 boundary points, 0.07 percent error in conductance calculation, 1.8 seconds computation time on a GE 635 computer) indicate this technique to be faster than various published techniques on computation time versus accuracy basis. The technique is applicable to structures with boundaries consisting of straight lines and circular arcs, multiply-connected, multiterminal, and open structures.

H.K. Gummel

Papers

An integral charge control model of bipolar transistors

MOTIS-An MOS timing simulator

Transition region capacitance of diffused p-n junctions

Thermal capture of electrons in silicon

A boundary technique for calculation of distributed resistance