(1987). Atoms, Radiation and Radiation Protection. International Journal of Radiation Biology and Related Studies in Physics, Chemistry and Medicine: Vol. 51, No. 5, pp. 951-951.

Atoms, Radiation and Radiation Protection

Cmos: Circuit Design, Layout, And Simulation

Owing to the impact of process voltage and temperature variations, the design of low-power low-pass filters (LPFs) with improved linearity is still one of the most challenging tasks for effective biological signal processing. This paper presents the design of a fourth-order Class-AB enhanced flipped source follower (EFSF) LPF circuit aimed at the detection of electroencephalography signals. The simulated results attained using complementary metal-oxide-semiconductor 180 nm technology node in Cadence Analog Design Environment demonstrate that the EFSF LPF emulates a DC-gain of -88 mdB with a bandwidth of 100 Hz and consumes 0.342 nW power from a supply voltage of 0.5 V. The calculated figure of merit for the proposed filter is 5.983 × 10-15 J with a dynamic range (DR) of 43.54 dB and input-referred noise of 91 µVrms. It consumes an area of 0.0458 mm2. To check the robustness of the proposed filter circuit, we performed Monte Carlo simulations with 200 runs. The statistical results achieved for the DC-gain, DR, and total harmonic distortion of the proposed filter show mean values of -188.09 mdB, 43.10 dB, and -41.85 dB along with standard deviation values of 285.21 mdB, 718.72 mdB, and 4.52 dB, respectively. The proposed Class-AB EFSF LPF can be used to achieve high power efficiency in future low-voltage and low-power biological systems.

0.342 nW Class-AB enhanced flipped source follower low pass filter for biomedical applications.

In this paper, we propose an accurate and computationally efficient Gradient Boosting approach for the estimation of statistical variations aware leakage power and propagation delay in the CMOS/FinFET standard digital cells. The proposed model estimates the leakage power and propagation delay w.r.t variations in process, temperature (−55°C to 125°C) and supply voltage(±10% variations). The distinguishing feature of the proposed approach is its compatibility with both CMOS and FinFET technologies. Moreover, the performance of the proposed model is consistent with various technology nodes. Exhaustive tests report an average error of <1% in 16nm CMOS and FinFET standard digital cells w.r.t analog HSPICE simulations with several orders increase in computational speed. Further, the complex cell estimation can be carried out through precharacterized standard cells abstaining longer simulations.

An Efficient Gradient Boosting Approach for PVT Aware Estimation of Leakage Power and Propagation Delay in CMOS/FinFET Digital Cells

An oscillator is an electronic device that used for the aim of generating a signal or waveform. Applications vary from clock generation in microprocessors to carrier synthesis in cellular telephones, requiring vastly different oscillators, oscillators’ topologies and performance parameters. VCO can be built using many circuit techniques. This paper deals with the design and implementation of Current Starved voltage controlled oscillators (CSVCO) using 45nm CMOS technology. CMOS circuitry in VLSI dissipates less power when static, and is denser than other implementations having same functionality. A VCO is an oscillator, where the control voltage controls the oscillator output frequency. The simulation of CSVCO is done in LT-Spice

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Analysis of Current Starved VoltageControlled Oscillator using 45nm CMOSTechnology

Design of amplifier circuits with low-noise operable at low-power to be used, especially for implantable neural interfaces, remains a huge challenge. This research paper presents the design of a low-noise low-voltage neural recording amplifier suitable for amplifying local field potentials and extracellular action potentials so as to meet the end requirement of an implantable neuro-medical system. Critical performance parameters of the smaller circuit blocks of the complete neural amplifier architecture have been found with the help of detailed mathematical analysis and then verified by the simulations conducted using 0.18 µm 4M1P foundry Semi-conductor Laboratory N-well process. The neural amplifier design proposed in this paper passes neural signal of interest with a mid-band gain of 49.9 dB over a bandwidth of 5.3 Hz-8.6 kHz, draws only 11.5 µW of power from ±0.9 V supply voltage, and exhibits an input-referred noise of 2.6 µVrms with a noise efficiency factor of 2.27. The area consumed by the proposed neural amplifier architecture is 0.192 mm2. The complete circuit design carried out in this paper should prove to be useful in equipment for the diagnosis of neurological disorders.

Design of a low-noise low-voltage amplifier for improved neural signal recording.

Technology scaling below 22 nm has brought several detrimental effects such as increased short channel effects (SCEs) and leakage currents. In deep submicron technology further scaling in gate length and oxide thickness can be achieved by changing the device structure of MOSFET. For 10–30 nm channel length multigate MOSFETs have been considered as most promising devices and FinFETs are the leading multigate MOSFET devices. Process parameters can be varied to obtain the desired performance of the FinFET device. In this paper, evaluation of on-off current ratio ( ), subthreshold swing (SS) and Drain Induced Barrier Lowering (DIBL) for different process parameters, that is, doping concentration (1015/cm3 to 1018/cm3), oxide thickness (0.5 nm and 1 nm), and fin height (10 nm to 40 nm), has been presented for 20 nm triangular FinFET device. Density gradient model used in design simulation incorporates the considerable quantum effects and provides more practical environment for device simulation. Simulation result shows that fin shape has great impact on FinFET performance and triangular fin shape leads to reduction in leakage current and SCEs. Comparative analysis of simulation results has been investigated to observe the impact of process parameters on the performance of designed FinFET.

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Comparative Simulation Analysis of Process Parameter Variations in 20 nm Triangular FinFET

Single-event effects (SEEs) have been the primary concern in study of radiation effects since late 1970s with the discovery of soft errors in terrestrial and space environments. The interaction of a single ionized particle with electronic devices leads to SEEs. In this paper, single-event upset (SEU) on CMOS devices in designing of a voltage-controlled oscillator (VCO) is analysed. Further, mitigation approaches of SEU are also discussed. To observe the impact of radiation, a VCO was designed in Cadence Virtuoso, and GDSII file of one ring oscillator stage was extracted to incorporate the same design in Silvaco MaskViews. With the help of layer map information file, masks were identified and used to design the CMOS inverter structure file for simulation of SEU condition. The input parameters for SEU simulation were evaluated from linear energy transfer (LET) graph of heavy ion under space conditions. The current profile of CMOS inverter was extracted under influence of a high-energy particle with the help of LET graph of that particle. This current profile was applied to different nodes of VCO and upset conditions were identified. Further, the impact of upset conditions on lock stage of phase-locked loop (PLL) is discussed. Results show that the SEU has significant impact on the logic state of inverters used in ring oscillator stage compared with current starving/biasing stage. The current profile of CMOS device has strong dependence on the energy of ion, its track, angle of incidence and the material. When angle of incidence is very less (
 $$7^{\circ }-14^{\circ }$$
 ) the channel will be occupied by a funnel of charge and it leads to the maximum degradation of device. This work shows that a device operating at high frequency is more susceptible to SEU. Triple modular redundancy (TMR) and Radiation Hardened By Design (RHBD) can be used to mitigate SEU. TMR consumes more power and is less accurate compared with the RHBD approach.

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Modelling and mitigation of single-event upset in CMOS voltage-controlled oscillator

Background & Aims There is a need for a real-time objective tool to assess the mucosal health of the gastrointestinal (GI) tract during endoscopy. Our aim was to develop, design, and validate a low-cost mucosal impedance (MI) device and determine its role in differentiating diseased mucosa from normal mucosa. Methods A biocompatible catheter was designed and developed after multiple iterations. It was validated with a commercially available catheter and histopathological analysis in a blinded manner. Patients undergoing resection of the GI tract were recruited after consent, and the resected specimens were analyzed ex vivo for MI within 10 minutes of resection. An average of 3 MI readings of the visually diseased segment and adjacent normal segment were analyzed. MI values of diseased and non-diseased mucosa were compared. Results The in-house catheter was validated with a commercially available impedance measuring device. It showed a high degree of positive correlation (rho = 0.616; P < 0.001). Two hundred and thirty-two patients (age 46 ± 15 years; 68% females) (180 inflammatory and 52 malignant pathology) who were undergoing abdominal surgery were enrolled. The median impedance value of diseased segments was significantly lower than that of the adjacent normal segments of gut in 130 paired samples [1832(727)Ω vs 2604(1295)Ω; P < 0.001]. The MI value of segments containing malignant tissue (n = 50) and inflamed tissue (n = 80) was significantly lower than the MI value of adjacent normal segments of the GI tract [1880(977)Ω vs 2583(1431)Ω; P < 0.001 and 1787(557)Ω vs 2515(1244)Ω; P < 0.001, respectively]. There was a 24% reduction in visually diseased segments [median reduction 712(661)Ω] from adjacent normal segments. A biocompatible endoscopic catheter (3-mm diameter) has been developed and tested in 3 patients and was found to differentiate diseased from normal mucosa. Conclusion Impedance spectroscopy is an effective real-time, simple, objective tool to differentiate diseased gut mucosa from healthy mucosa. 

H. S. Jatana

Papers

Design of a low-noise low-voltage amplifier for improved neural signal recording.

Comparative Simulation Analysis of Process Parameter Variations in 20 nm Triangular FinFET

Modelling and mitigation of single-event upset in CMOS voltage-controlled oscillator

Mucosal impedance spectroscopy: for objective real time assessment of mucosal health