The temporal read noise on the signal path of a complementary metal-oxide semiconductor image sensor is analyzed to investigate the effectiveness of high-gain column amplifiers in enhancing sensor sensitivity. The signal path examined includes a pixel source follower, a switched-capacitor, noise-cancelling, high-gain amplifier, and a sample-and-hold circuit in each column. It is revealed that the total random readout noise consists of a component due to noise charge sampled and held at the charge summation node of the amplifier and transferred to the output, and a direct noise component sampled at the sample-and-hold stage at the output of the column amplifier. The analysis suggests that the direct noise components can be greatly reduced by increasing the column amplifier gain, indicating that an extremely low-noise readout circuit may be achievable through the development of a double-stage noise-cancelling architecture.

Noise analysis of high-gain, low-noise column readout circuits for CMOS image sensors

A low temporal noise and high dynamic range CMOS image sensor is developed. A 1Mpixel CMOS image sensor with column-parallel folding-integration and cyclic ADCs has 80μVrms (1.2e-) temporal noise, 82 dB dynamic range using 64 samplings in the folding-integration ADC mode. Very high variable gray-scale resolution of 13b through 19b is attained by changing the number of samplings of pixel outputs. The implemented CMOS image sensor using a 0.18-μm technology has the sensitivity of 10-V/lx·s, the conversion gain of 67- μV/e-, and linear digital code range of more than 4 decades.

A Low-Noise High Intrascene Dynamic Range CMOS Image Sensor With a 13 to 19b Variable-Resolution Column-Parallel Folding-Integration/Cyclic ADC

A high-speed analog VLSI image acquisition and pre-processing system has been designed and fabricated in a 0.35 ?m standard CMOS process. The chip features a massively parallel architecture enabling the computation of programmable low-level image processing in each pixel. Extraction of spatial gradients and convolutions such as Sobel or Laplacian filters are implemented on the circuit. For this purpose, each 35 ?m × 35 ?m pixel includes a photodiode, an amplifier, two storage capacitors, and an analog arithmetic unit based on a four-quadrant multiplier architecture. The retina provides address-event coded output on three asynchronous buses: one output dedicated to the gradient and the other two to the pixel values. A 64 × 64 pixel proof-of-concept chip was fabricated. A dedicated embedded platform including FPGA and ADCs has also been designed to evaluate the vision chip. Measured results show that the proposed sensor successfully captures raw images up to 10 000 frames per second and runs low-level image processing at a frame rate of 2000 to 5000 frames per second.

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A 10 000 fps CMOS Sensor With Massively Parallel Image Processing

A high-sensitivity CMOS image sensor using gain-adaptive column amplifiers is presented and tested. The use of high gain for the column amplifier reduces input-referred random noise, and when coupled with a column-based digital noise cancellation technique, also reduces fixed pattern noise. An experimental application of the circuit using 0.25-/spl mu/m CMOS technology with pinned photodiodes gave an rms random noise of 263 /spl mu/V and an rms fixed pattern noise of 50 /spl mu/V.

A high-sensitivity CMOS image sensor with gain-adaptive column amplifiers

For low-noise complementary metal-oxide-semiconductor (CMOS) image sensors, the reduction of pixel source follower noises is becoming very important Column-parallel high-gain readout circuits are useful for low-noise CMOS image sensors This paper presents column-parallel high-gain signal readout circuits, correlated multiple sampling (CMS) circuits and their noise reduction effects In the CMS, the gain of the noise cancelling is controlled by the number of samplings It has a similar effect to that of an amplified CDS for the thermal noise but is a little more effective for 1/f and RTS noises Two types of the CMS with simple integration and folding integration are proposed In the folding integration, the output signal swing is suppressed by a negative feedback using a comparator and one-bit D-to-A converter The CMS circuit using the folding integration technique allows to realize a very low-noise level while maintaining a wide dynamic range The noise reduction effects of their circuits have been investigated with a noise analysis and an implementation of a 1Mpixel pinned photodiode CMOS image sensor Using 16 samplings, dynamic range of 594 dB and noise level of 19 e(-) for the simple integration CMS and 75 dB and 22 e(-) for the folding integration CMS, respectively, are obtained

https://www.mdpi.com/1424-8220/10/10/9139/pdf

Column-parallel correlated multiple sampling circuits for CMOS image sensors and their noise reduction effects.

A 0.25 /spl mu/m technology CMOS image sensor employs a 4.2 /spl mu/m pitch pinned-photodiode pixel. A column amplifier and digital domain processing reduce the fixed pattern noise to 55 /spl mu/V. The saturation voltage is 1 V with a 2.5 V supply voltage, and the dynamic range is 69 dB.

H. Satoh

Papers

A high-sensitivity CMOS image sensor with gain-adaptive column amplifiers

A column-based pixel-gain-adaptive CMOS image sensor for low-light-level imaging