0.7-V supply, 21-nW All–MOS voltage reference using a MOS-Only current-driven reference core in digital CMOS

In this paper, a novel non-bandgap CMOS voltage reference with sub one-volt power supply is proposed and simulated in 0.18 μm standard CMOS technology. Thermal voltage obtained from ∆VBE with positive and threshold voltage of a nMOS transistor with negative temperature coefficient are utilized to achieve a stable-temperature voltage reference. A current proportional-to- threshold voltage and a current proportional-to-absolute-temperature are used to produce positive and negative temperature coefficient parts. The reference voltage is obtained from the proper combination of these two parts. The nominal output voltage reference is about 0.5-V with the temperature coefficient of 36 ppm/ °C across a temperature range of 0–120 °C at 0.9-V of supply. The power supply noise attenuation of 84 dB is achieved without any filtering capacitor below 15 Hz at 1-V of Vdd.

Sub 1-V supply voltage-reference based on mutual temperature cancellation of VT and VTH

The well-controlled exponential ID(VS) characteristics of MOS transistors operating in weak inversion allows the realization of a very good bandgap reference compatible with CMOS technologies and operating with an input voltage as low as 1.3 V. Variations of less than 3 mV over more than 100oC have been obtained on a few samples and are certainly within reach for each circuit with an adjustment. The temperature range can be further extended by improving the design.

A Low-Voltage CMOS Bandgap Reference

The invention provides a phase interpolation type clock recovering circuit for summating sampling voltage. The phase interpolation type clock recovering circuit comprises a CLKI input end, a CLKQ input end, a first rising edge sampling keeping circuit, a first falling edge sampling keeping circuit, a second rising edge sampling keeping circuit, a second falling edge sampling keeping circuit, a first summating circuit, a second summating circuit and a phase interpolation circuit, wherein the CLKI input end is connected with the first rising edge sampling keeping circuit, the first falling edge sampling keeping circuit and the phase interpolation circuit respectively; the first rising edge sampling keeping circuit and the first falling edge sampling keeping circuit are connected with the input end of the first summating circuit; the output end of the first summating circuit is connected with the phase interpolation circuit. According to the phase interpolation type clock recovering circuit, the summating circuits are additionally arranged between the sampling keeping circuits and the phase interpolation circuit and data input into the phase interpolation circuit are average values of variable quantities of the upper and lower edges, so that the shake becomes small and the phase stability of recovering a clock is improved.

Phase interpolation type clock recovering circuit for summating sampling voltage

Ionic Polymer Metal Composites (IPMCs) are a group of electroactive polymer materials that exhibit a large deformation due to the application of low voltages resulting from the movement of cations inside the polymer. These materials have many applications in various fields such as Micro-robotics, biomedical engineering equipment and artificial muscles. Due to the possibility of producing these materials in micro dimensions they can also be used in micro-electromechanical systems. On the other hand, due to their sensitivity to very low voltages, they can be a good substitute for silicon in micro-electromechanical systems. In the present study, the dynamical analysis of a micro-beam fixed at two ends made of these materials is investigated using electrical-chemical-mechanical relations. COMSOL Multiphysics software is used to solve the relations. The results showed that for harmonic stimulation (sinusoidal voltage) the system experiences only the same form of the first mode. It was also observed that increasing the frequency would decrease the amplitude of the micro-beam oscillation.

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Analysis and Study of the Nonlinear Electrodynamics Behaviour of a Micro-beam Made of Ionic Polymer Metal Composite (IPMC)

A nano-watt bandgap voltage reference (BGR) is presented. To provide a low-voltage and low-power BGR, the circuit has been biased in the sub-threshold region; thereby, drawing a few nano-amperes current from the source, has been achieved. In order to reduce die area and also power consumption, instead of resistor, transistor is used. To generate PTAT voltage, self-cascode composite structure is used for the transistors. The results from post-layout simulation using 0.18-μm standard CMOS technology show that the proposed BGR circuit generates a reference voltage of 625 mV, obtaining temperature coefficient of 13 ppm/ °C in the temperature range of − 25 °C to 110 °C. The simulated power supply rejection ratio is 42 dB. Fully designed with MOS transistors, the circuit draws 18 nA from a 0.9-V supply. The active area of the proposed BGR is 0.00067 mm2.

A 0.9-V supply, 16.2 nW, fully MOSFET resistorless bandgap reference using sub-threshold operation

This paper proposes a novel low-power burst-mode clock recovery circuit (CRC) based on analog phase interpolator (PI) Accordingly, we employed a new configuration for PI-based CRC in which a novel architecture is utilized for double-edge triggered sample-and-hold (DT-SH) In the proposed DT-SH one buffer is shared between two single-edge triggered SH (ST-SH) resulting in great reduction of total power consumption as well as design complexity and die area Verifying functionality of proposed PI-based CRC, the circuit is designed and simulated in 018-μm CMOS technology As simulation results show, the proposed CRC recovers clock at 5GHz in the first unit interval of input data where approximately 40% reduction in power dissipation is achieved The circuit consumes 254mW power from a 18-V supply

Low-power burst-mode clock recovery circuit using analog phase interpolator

This paper presents an ultra-wideband (UWB) transmitter based on capacitive array that decreases dependency of data rate to pulse repetition frequency, as well as power consumption and complexity. The entire system includes several delay stages, a capacitive array circuit, a Schmitt trigger, an impulse generator, a cross-coupled oscillator, and an antenna driver. A sequence of 5-bit parallel data is applied to the capacitive array, providing ramp signals with 32 equally separated slopes. This returns a variable pulsewidth at the output of the Schmitt trigger circuit, which corresponds to a specific sequence of input data. Post-layout simulation results show that the proposed circuit provides a linear time change in the pulsewidth with an accuracy of 176 ps in average for every input data LSB. Furthermore, the entire circuit consumes only 190 µW from a 0.6-V supply. The proposed transmitter achieves a significantly low energy consumption of 950 fJ/bit at 200 Mbps within the Federal Communications Commission spectral mask which addresses the design challenges of ultralow-power internet-of-things devices. The circuit is designed in TSMC 65-nm standard CMOS technology and occupies 0.0525 mm2of die area.

Hadi Hayati

Papers

A 0.9-V supply, 16.2 nW, fully MOSFET resistorless bandgap reference using sub-threshold operation

Low-power burst-mode clock recovery circuit using analog phase interpolator

An Ultralow-Power Capacitive Array-Based IR-UWB Transmitter Using Cross-Coupled Oscillator