The compelling demand for higher performance and lower power consumption in electronic systems is the main driving force of the electronics industry's quest for devices and/or architectures based on new materials. Here, we provide a review of electronic devices based on two-dimensional materials, outlining their potential as a technological option beyond scaled complementary metal-oxide-semiconductor switches. We focus on the performance limits and advantages of these materials and associated technologies, when exploited for both digital and analog applications, focusing on the main figures of merit needed to meet industry requirements. We also discuss the use of two-dimensional materials as an enabling factor for flexible electronics and provide our perspectives on future developments.

Electronics based on two-dimensional materials

Steep subthreshold swing transistors based on interband tunneling are examined toward extending the performance of electronics systems. In particular, this review introduces and summarizes progress in the development of the tunnel field-effect transistors (TFETs) including its origin, current experimental and theoretical performance relative to the metal-oxide-semiconductor field-effect transistor (MOSFET), basic current-transport theory, design tradeoffs, and fundamental challenges. The promise of the TFET is in its ability to provide higher drive current than the MOSFET as supply voltages approach 0.1 V.

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Low-Voltage Tunnel Transistors for Beyond CMOS Logic

International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －

In the quest for higher performance, the dimensions of field-effect transistors (FETs) continue to decrease. However, the reduction in size of FETs comprising 3D semiconductors is limited by the rate at which heat, generated from static power, is dissipated. The increase in static power and the leakage of current between the source and drain electrodes that causes this increase, are referred to as short-channel effects. In FETs with channels made from 2D semiconductors, leakage current is almost eliminated because all electrons are confined in atomically thin channels and, hence, are uniformly influenced by the gate voltage. In this Review, we provide a mathematical framework to evaluate the performance of FETs and describe the challenges for improving the performances of short-channel FETs in relation to the properties of 2D materials, including graphene, transition metal dichalcogenides, phosphorene and silicene. We also describe tunnelling FETs that possess extremely low-power switching behaviour and explain how they can be realized using heterostructures of 2D semiconductors. Field-effect transistors (FETs) with semiconducting channels made from 2D materials are known to have fewer problems with short-channel effects than devices comprising 3D semiconductors. In this Review, a mathematical framework to evaluate the performance of FETs is outlined with a focus on the properties of 2D materials, such as graphene, transition metal dichalcogenides, phosphorene and silicene.

Two-dimensional semiconductors for transistors

This review paper explores considerations for ultimate CMOS transistor scaling Transistor architectures such as extremely thin silicon-on-insulator and FinFET (and related architectures such as TriGate, Omega-FET, Pi-Gate), as well as nanowire device architectures, are compared and contrasted Key technology challenges (such as advanced gate stacks, mobility, resistance, and capacitance) shared by all of the architectures will be discussed in relation to recent research results

Considerations for Ultimate CMOS Scaling

Unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal walls, and methods of fabricating unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal walls, are described. An integrated circuit structure (640) includes a first semiconductor fin having a cut along a length of the first semiconductor fin. A second semiconductor fin has a cut along a length of the second semiconductor fin. A gate endcap isolation structure (650) is between the first semiconductor fin and the second semiconductor fin. The gate endcap isolation structure has a substantially uniform width along the lengths of the first and second semiconductor fins.

Unidirectional self-aligned gate endcap (sage) architectures with gate-orthogonal walls

Embodiments herein describe techniques, systems, and method for a semiconductor device. Embodiments herein may present a semiconductor device having a channel area including a channel III-V material, and a source area including a first portion and a second portion of the source area. The first portion of the source area includes a first III-V material, and the second portion of the source area includes a second III-V material. The channel III-V material, the first III-V material and the second III-V material may have a same lattice constant. Moreover, the first III-V material has a first bandgap, and the second III-V material has a second bandgap, the channel III-V material has a channel III-V material bandgap, where the channel material bandgap, the second bandgap, and the first bandgap form a monotonic sequence of bandgaps. Other embodiments may be described and/or claimed.

Schottky diode structures and integration with iii-v transistors

A device includes a first Group III-Nitride (III-N) material, a gate electrode above the III-N material, and the gate electrode. The device further includes a tiered field plate, suitable for increasing gate breakdown voltage with minimal parasitics. In the tiered structure, a first plate is on the gate electrode, the first plate having a second sidewall laterally beyond a sidewall of the gate, and above the III-N material by a first distance. A second plate on the first plate has a third sidewall laterally beyond the second sidewall and above the III-N material by a second distance, greater than the first. A source structure and a drain structure are on opposite sides of the gate electrode, where the source and drain structures each include a second III-N material.

Self aligned gate connected plates for group iii-nitride devices and methods of fabrication

Embodiments of the invention include an electromagnetic waveguide and methods of forming the electromagnetic waveguide. In an embodiment the electromagnetic waveguide includes a first spacer and a second spacer. In an embodiment, the first and second spacer each have a reentrant profile. The electromagnetic waveguide may also include a conductive body formed between in the first and second spacer, and a void formed within the conductive body. In an additional embodiment, the electromagnetic waveguide may include a first spacer and a second spacer. Additionally, the electromagnetic waveguide may include a first portion of a conductive body formed along sidewalls of the first and second spacer and a second portion of the conductive body formed between an upper portion of the first portion of the conductive body. In an embodiment, the first portion of the conductive body and the second portion of the conductive body define a void through the electromagnetic waveguide.

Monolithic splitter using re-entrant poly silicon waveguides

Embodiments disclosed herein include nanoribbon and nanowire semiconductor devices. In an embodiment, the semiconductor device comprises a nanowire disposed above a substrate. In an embodiment, the nanowire has a first dopant concentration, and the nanowire comprises a pair of tip regions on opposite ends of the nanowire. In an embodiment, the tip regions comprise a second dopant concentration that is greater than the first dopant concentration. In an embodiment, the semiconductor device further comprises a gate structure over the nanowire. In an embodiment, the gate structure is wrapped around the nanowire, and the gate structure defines a channel region of the device. In an embodiment, a pair of source/drain regions are on opposite sides of the gate structure, and both source/drain regions contact the nanowire.

Hafez Walid M

Papers

Unidirectional self-aligned gate endcap (sage) architectures with gate-orthogonal walls

Schottky diode structures and integration with iii-v transistors

Self aligned gate connected plates for group iii-nitride devices and methods of fabrication

Monolithic splitter using re-entrant poly silicon waveguides

Long channel nanowire transistors for soc applications