Hafez Walid M

TL;DR: In this paper, a transistor including a source and a drain each formed in a substrate, a channel disposed in the substrate between the source and drain, wherein the channel includes opposing sidewalls with a distance between the opposing sidewall defining a width dimension of the channel and wherein the opposing sides extend a distance below a surface of the substrate; and a gate electrode on the channel.

TL;DR: In this paper, a non-planar transistor consisting of a fin and a gate dielectric is described, with at least one of the channel region width being wider than the source region width.

Abstract: Techniques are disclosed for forming semiconductor structures including resistors between gates on self-aligned gate edge architecture. A semiconductor structure includes a first semiconductor fin extending in a first direction, and a second semiconductor fin adjacent to the first semiconductor fin, extending in the first direction. A first gate structure is disposed proximal to a first end of the first semiconductor fin and over the first semiconductor fin in a second direction, orthogonal to the first direction, and a second gate structure is disposed proximal to a second end of the first semiconductor fin and over the first semiconductor fin in the second direction. A first structure comprising isolation material is centered between the first and second semiconductor fins. A second structure comprising resistive material is disposed in the first structure, the second structure extending at least between the first gate structure and the second gate structure.

TL;DR: In this article, a transistor including a channel disposed between a source and a drain, a gate electrode disposed on the channel and surrounding the channel, where the source and the drain are formed in a body on a substrate and the channel is separated from the body.

TL;DR: In this paper, the authors describe a nanowire and nanoribbon device with non-uniform dielectric thicknesses, where a substrate and a plurality of first semiconductor layers are arranged in a vertical stack over the substrate.