Chang Hsu-Yu

TL;DR: A leading edge 14 nm SoC platform technology based upon the 2nd generation Tri-Gate transistor technology has been optimized for density, low power and wide dynamic range and a full suite of analog, mixed-signal and RF features are supported.

TL;DR: In this article, an impurity source film is formed along a portion of a non-planar semiconductor fin structure, which is used to serve as source of impurity that becomes electrically active subsequent to diffusing from the source film into the semiconductor Fin.

TL;DR: In this paper, the transistor reliability characterization of a 14nm System-on-Chip (SoC) node optimized for low power operation is described, and in-depth assessments of reliability and performance for Core and I/O devices are performed on Logic and SoC nodes, and clear trends with scaling are identified.

TL;DR: In this paper, a gate metal work function is graduated between source and drain edges of the gate electrode for improved high voltage performance, and a high voltage transistor with graduated gate metal thickness is integrated with another transistor employing a gate electrode metal of nominal thickness.

TL;DR: In this paper, a MOS antifuse with an accelerated dielectric breakdown induced by a void or seam formed in the electrode is presented, where the programming voltage at which the MOS anti-antifuse undergoes deformation is reduced through intentional damage.