Doo-Sub Lee

TL;DR: The use of barrier-engineered materials and gate all-around structure in the 3D V-NAND cell exhibits advantages over 1 × nm planar NAND, such as small Vth shift due to small cell coupling and narrow natural Vth distribution.

TL;DR: A 48 WL stacked 256-Gb V-NAND flash memory with a 3 b MLC technology withDual state machine architecture is proposed to achieve optimal timing for BL and WL, respectively and an embedded ZQ calibration technique with temperature compensation is introduced.

TL;DR: The previously used node-shrinking methodology is facing challenges due to increased cell-to-cell interference and patterning difficulties caused by decreasing dimension, so 3D-stacking technology has been developed.

TL;DR: The result of long and focused research in 3D stacking technology is developing 128 Gb 3b/cell Vertical NAND with 32 stack WL layers for the first time, which is the smallest128 Gb NAND Flash.

TL;DR: A 64-Mbit bidirectional data strobed, double-data-rate SDRAM achieves a peak bandwidth of 2.56 GByte/s on a 64-bit-channel, 256-MByte memory system at V/sub cc/=3.3 V and T=25/spl deg/C.