Jinman Han

TL;DR: In this article, the erasing method applies a word line erase voltage to a plurality of word lines connected to the memory cells respectively, applies a specific voltage to the ground selection line connected to a ground selection transistor, and floats the ground line in response to a voltage change of the substrate.

TL;DR: The use of barrier-engineered materials and gate all-around structure in the 3D V-NAND cell exhibits advantages over 1 × nm planar NAND, such as small Vth shift due to small cell coupling and narrow natural Vth distribution.

TL;DR: In this article, the operating method of a data storage device includes storing data in the buffer memory according to an external request, and determining whether the data stored in buffer memory is data accompanying a buffer program operation of the memory cell array.

TL;DR: A monolithic 64 Gb MLC NAND flash based on 21 nm process technology has been developed and features a newly developed asynchronous DDR interface that can support up to the maximum bandwidth of 400 MB/s.

TL;DR: This paper describes a 32-bank 1 Gb DRAM achieving 1 Gbyte/s (500 Mb/s/DQ pin) data bandwidth and the access time from RAS of 31 ns at V/sub cc/=2.0 V and 25/spl deg/C.