This paper presents an alternate test implementation based on model redundancy that permits to achieve lower prediction errors than a classical implementation, even if training is performed over a small set of devices. The idea is to build different regression models for each specification during the training phase, and then to verify prediction consistency between the different models during the production testing phase. In case of divergent predictions, the devices are removed from the alternate test tier and directed to a second tier where further testing may apply. The approach is illustrated on a real case study that employs production test data from an RF power amplifier. Results show that, on the contrary to the classical implementation where prediction accuracy degrades when reducing the training set size, the proposed approach permits to preserve prediction accuracy independently of the training set size, while only a very small number of devices are directed to the second tier of the test flow.

Making predictive analog/RF alternate test strategy independent of training set size

The accepted approach in industry today to ensure out-going quality in high-volume manufacturing of analog circuits is to directly measure datasheet specifications. To reduce the involved costs it is required to eliminate specification tests or use instead lower-cost alternative tests. However, this is too risky if the resultant fault coverage and yield coverage metrics of the new test approach are not estimated accurately. This paper proposes a methodology to efficiently derive a set of most probable failing and marginally functional circuit instances. Based on this set, we can readily define and estimate fault coverage and yield coverage metrics. Our methodology reduces the required number of Monte Carlo simulations by one or more orders of magnitude. As an illustrative example, the methodology is applied to a radio frequency low-noise amplifier.

Fast Monte Carlo-Based Estimation of Analog Parametric Test Metrics

Testing the static performances of high-resolution analog-to-digital converters (ADCs) consumes long test times that are disproportionately high with respect to the test time devoted to other types of circuits embedded in a modern system-on-chip (SoC). In this paper, we review the state-of-the-art of reduced-code linearity test methods for pipeline ADCs and we propose a new approach that increases the efficiency and accuracy of the method. We show that by exploiting some inherent properties in the architecture of pipeline ADCs we can achieve significant static test time reduction while maintaining the accuracy of the standard histogram test. The proposed method is demonstrated on a 55 nm 11-bit 2.5-bits/stage pipeline ADC.

Exploiting Pipeline ADC Properties for a Reduced-Code Linearity Test Technique

Accurate and efficient evaluation of alternative test methods is required for analog/mixed-signal circuits. To address this need, this article presents a semiautomated practical simulation flow specifically targeting circuits with long simulation times.

Practical Simulation Flow for Evaluating Analog/Mixed-Signal Test Techniques

This work presents an efficient on-chip ramp generator targeting to facilitate the deployment of Built-In Self-Test (BIST) techniques for ADC static linearity characterization. The proposed ramp generator is based on a fully-differential switched-capacitor integrator that is conveniently modified to produce a very small integration gain, such that the ramp step size is a small fraction of the LSB of the target ADC. The proposed ramp generator is employed in a servo-loop configuration to implement a BIST version of the reduced-code linearity test technique for pipeline ADCs, which drastically reduces the volume of test data and, thereby, the test time, as compared to the standard test based on a histogram. The demonstration of the pipeline ADC BIST is carried out based on a mixture of transistor-level and behavioral-level simulations that employ actual production test data.

A 65nm CMOS Ramp Generator Design and its Application Towards a BIST Implementation of the Reduced-Code Static Linearity Test Technique for Pipeline ADCs

The deployment of alternative, low-cost RF test methods in industry has been, to date, rather limited. This is due to the potentially impaired ability to identify device pass/fail labels when departing from traditional specification test. By relying on alternative tests, pass/fail labels must be derived indirectly through new test limits defined for the alternative tests, which may incur error in the form of test escapes or yield loss. Clearly, estimating these test metrics as early as possible in the test development process is key to the success of an alternative test approach. In this work, we employ a test metrics estimation technique based on non-parametric kernel density estimation to obtain such early estimates, and, for the first time, demonstrate a real-world case study of test metric estimation efficiency at parts-per-million levels. To achieve this, we employ a set of more than 1 million RF devices fabricated by Texas Instruments, which have been tested with both traditional specification tests as well as alternative, low-cost On-chip RF Built-in Tests, or "ORBiTs".

/pdf/on-proving-the-efficiency-of-alternative-rf-tests-lukqey96f2.pdf

On proving the efficiency of alternative RF tests

Reduced code testing of a pipeline analog-to-digital converter (ADC) consists of inferring the complete static transfer function by measuring the width of a small subset of codes. This technique exploits the redundancy that is present in the way the ADC processes the analog input signal. The main challenge is to select the initial subset of codes such that the widths of the rest of the codes can be estimated correctly. By applying the state-of-the-art technique to a real 11-bit 2.5-bit/stage, 55nm pipeline ADC, we observed that the presence of noise affected the accuracy of the estimation of the static performances (e.g, differential nonlinearity and integral non-linearity). In this paper, we exploit another feature of the redundancy to cancel out the effect of noise. Experimental measurements demonstrate that this reduced code testing technique estimates the static performances with an accuracy equivalent to the standard histogram technique. Only 6 % of the codes need to be considered which represents a very significant test time reduction.

Reduced code linearity testing of pipeline adcs in the presence of noise

Over the past decade, interest has increased in leveraging low-cost "alternate" test methods as a drop-in replacement for testing analog and RF devices. The current practice for testing such devices, known as specification test, can be very expensive by comparison. By substituting less-costly alternate tests for specification test, substantial test cost reduction can be achieved. Despite this promised cost reduction, the testing community has been reluctant to adopt such alternate test methods in industrial settings, as the error incurred by alternate test can be quite difficult to capture. Estimating the expected test error metrics early in the fabrication process is, therefore, extremely desirable. In this work, we present a case study in which we investigate the reliability of kernel density estimation as a means of providing such early estimates of alternate test error. We also introduce the novel application of Laplacian score feature selection to identify key subsets of alternate tests. With these tools we are able to dramatically reduce the number of alternate tests applied, as well as predict test escape and yield loss error metrics within about 0.5% of their true values when evaluated on an industrial dataset with more than 1 million devices.

PPM-accuracy Error Estimates for Low-Cost Analog Test: A Case Study

This paper presents an evaluation of built-in test sensors for measuring the response of a Radio Frequency Low Noise Amplifier. These sensors provide low frequency or DC test measurements that can be used for low-cost on-chip or off-chip test. First, a variety of test measurements are evaluated by considering parametric test metrics (e.g. defect level and yield loss) and catastrophic fault coverage. Next, embedded sensors aimed at taking the selected measurements are presented. Finally, the test metrics of the overall chip are estimated at the schematic and the layout level.

Evaluation of built-in sensors for RF LNA response measurement

Unlike the top-down photolithographic CMOS VLSI process, cost-effective bulk fabrication of nanodevices calls for a bottom-up approach, generally called self-assembly. Self- assembly, however, inherently lends itself to innate disparities in the structure of nominally identical nanodevices and, consequently, wide inter-device variance in their functionality. As a result, nanodevice characterization and testing calls for a slow and tedious procedure involving a large number of measurements. In this work, we discuss a statistical approach which learns measurement correlations from a small set of fully characterized nanodevices and utilizes the extracted knowledge to simplify the process for the rest of the nanodevices. More specifically, we employ various machine-learning methods which rely on a small subset of measurements to (i) predict the performances of a fabricated nanodevice, (ii) decide whether a nanodevice passes or fails a given set of specifications, and (iii) bin a nanodevice with regards to several sets of increasingly strict specifications. The proposed methods are demonstrated and their effectiveness is assessed, within the context of nanowire-based chemical sensing, using a set of fabricated and fully characterized nanowires.

Haralampos Stratigopoulos

Papers

On proving the efficiency of alternative RF tests

Reduced code linearity testing of pipeline adcs in the presence of noise

PPM-accuracy Error Estimates for Low-Cost Analog Test: A Case Study

Evaluation of built-in sensors for RF LNA response measurement

A Statistical Approach to Characterizing and Testing Functionalized Nanowires