A signal under measurement x(t) is transformed into a complex analytic signal zc(t), and an instantaneous phase of the xc(t) is estimated using the zc(t). A linear phase is removed from the instantaneous phase to obtain a phase noise waveform Δ Ζ (t) of the x(t), and the Δ Ζ (t) is sampled at a timing close t o a zero-crossing timing of the x(t) to obtain a timing jitter sequence. Then a difference sequence of the timing jitter sequence is calculated to obtain a period jitter sequence. The period jitter sequence is multiplied by a ratio T0/Tk,k+1 of the fundamental period T0 of the x(t) and the sampling time interval Tk,k+1 to make a correction of the period jitter sequence. A period jitter value of the x(t) is obtained from the corrected period jitter sequence.

Apparatus for and method of measuring jitter

A video compensation system for analog video transmission is described. The compensation system is employed in an analog video switching circuit such that each time a conductive path is switched, the system automatically tests the new switch path for a new compensation value. The compensation value is determined by measuring the response of the new path to a set of tones that are applied to the conductive path, the response to which is measured against a table of responses previously recorded. The measured responses are compared to the recorded responses to determine an appropriate compensation control voltage, which is applied to an equalizer system. In an alternative embodiment, the skew compensations also provided between red, green, and blue twisted pair lines in the cables by performing comparative analysis between corresponding pairs of the red, green, and blue signals.

Automatic equalization of video signals

An integrated circuit capable of on-chip jitter tolerance measurement includes a jitter generator circuit to produce a controlled amount of jitter that is injected into at least one clock signal, and a receive circuit to sample an input signal according to the at least one clock signal. The sampled data values output from the receiver are used to evaluate the integrated circuit's jitter tolerance.

Integrated Circuit Having Receiver Jitter Tolerance ("JTOL") Measurement

Linearity testing of analog-to-digital converters (ADCs) is very challenging and expensive due to the stringent linearity requirement on the stimulus and the extremely long test time. This paper introduces a novel method for ADC static linearity testing, allowing the stimulus linearity requirement to be significantly relaxed and the test time to be significantly reduced compared to the state-of-art histogram method. Two nonlinear but functionally related input signals are used as the ADC’s excitation and a stimulus error removal technique is used to recover test accuracy. With a segmented non-parametric integral nonlinearity model, this method requires much fewer parameters to accurately represent the nonlinearity. The proposed algorithm has been extensively verified and correlated in simulations. This method not only enables low-cost production testing but can also be used for low-cost on-chip built-in self-test. This method is limited to ADCs with segmented architecture such as SAR ADCs, pipeline ADCs, and cyclic ADCs.

USER-SMILE: Ultrafast Stimulus Error Removal and Segmented Model Identification of Linearity Errors for ADC Built-in Self-Test

We propose a Built-In Self-Test (BIST) paradigm for analog and mixed-signal (A/M-S) Integrated Circuits (ICs), called symmetry-based BIST ( SymBIST ). SymBIST exploits inherent symmetries in an A/M-S IC to construct signals that are invariant by default, and subsequently checks those signals against a tolerance window. Violation of invariant properties points to the occurrence of a defect or abnormal operation. SymBIST is designed to serve as a functional safety mechanism. It is reusable ranging from post-manufacturing test, where it targets defect detection, to on-line test in the field of operation, where it targets low-latency detection of transient failures and degradation due to aging. We demonstrate SymBIST on a Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC). SymBIST features high defect coverage, short test time, low overhead, zero performance penalty, and has a fully digital interface making it compatible with modern digital test access mechanisms.

/pdf/symbist-symmetry-based-analog-and-mixed-signal-built-in-self-3elbev6p0x.pdf

SymBIST : Symmetry-Based Analog and Mixed-Signal Built-In Self-Test for Functional Safety

Testing the static performances of high-resolution analog-to-digital converters (ADCs) consumes long test times that are disproportionately high with respect to the test time devoted to other types of circuits embedded in a modern system-on-chip (SoC). In this paper, we review the state-of-the-art of reduced-code linearity test methods for pipeline ADCs and we propose a new approach that increases the efficiency and accuracy of the method. We show that by exploiting some inherent properties in the architecture of pipeline ADCs we can achieve significant static test time reduction while maintaining the accuracy of the standard histogram test. The proposed method is demonstrated on a 55 nm 11-bit 2.5-bits/stage pipeline ADC.

Exploiting Pipeline ADC Properties for a Reduced-Code Linearity Test Technique

This work presents an efficient on-chip ramp generator targeting to facilitate the deployment of Built-In Self-Test (BIST) techniques for ADC static linearity characterization. The proposed ramp generator is based on a fully-differential switched-capacitor integrator that is conveniently modified to produce a very small integration gain, such that the ramp step size is a small fraction of the LSB of the target ADC. The proposed ramp generator is employed in a servo-loop configuration to implement a BIST version of the reduced-code linearity test technique for pipeline ADCs, which drastically reduces the volume of test data and, thereby, the test time, as compared to the standard test based on a histogram. The demonstration of the pipeline ADC BIST is carried out based on a mixture of transistor-level and behavioral-level simulations that employ actual production test data.

A 65nm CMOS Ramp Generator Design and its Application Towards a BIST Implementation of the Reduced-Code Static Linearity Test Technique for Pipeline ADCs

The reduced code linearity test technique for pipeline ADCs consists in measuring some judiciously selected codes which contain the information about the linearity of the converter as opposed to the standard histogram technique that considers indiscriminately all codes. This technique dramatically reduces the static test time for pipeline ADCs. In this paper, we identify some limitations in the existing version of the technique and we provide solutions to enhance its accuracy. The enhanced technique is applied to a 12-bit 2.5-bit/stage pipeline ADC.

Enhanced reduced code linearity test technique for multi-bit/stage pipeline ADCs

The present invention relates to a method for determining a characteristic of a periodic digital signal, including the steps of: defining a measurement period such that the ratio between the measurement period and the period of the digital signal is a ratio of integers; selecting a set of measurement periods in which the digital signal has substantially the same phase; defining a measurement time having a same position in each measurement period of the set; storing the value of the digital signal at each measurement time; shifting the measurement time by a predetermined pitch lower than one measurement period; repeating the two preceding steps until the measurement time of each measurement period has scanned a predetermined portion of the measurement period; and analyzing the succession of the noted values.

Periodic signal digital testing

Reduced code testing of a pipeline analog-to-digital converter (ADC) consists of inferring the complete static transfer function by measuring the width of a small subset of codes. This technique exploits the redundancy that is present in the way the ADC processes the analog input signal. The main challenge is to select the initial subset of codes such that the widths of the rest of the codes can be estimated correctly. By applying the state-of-the-art technique to a real 11-bit 2.5-bit/stage, 55nm pipeline ADC, we observed that the presence of noise affected the accuracy of the estimation of the static performances (e.g, differential nonlinearity and integral non-linearity). In this paper, we exploit another feature of the redundancy to cancel out the effect of noise. Experimental measurements demonstrate that this reduced code testing technique estimates the static performances with an accuracy equivalent to the standard histogram technique. Only 6 % of the codes need to be considered which represents a very significant test time reduction.

Herve Naudet

Papers

Exploiting Pipeline ADC Properties for a Reduced-Code Linearity Test Technique

A 65nm CMOS Ramp Generator Design and its Application Towards a BIST Implementation of the Reduced-Code Static Linearity Test Technique for Pipeline ADCs

Enhanced reduced code linearity test technique for multi-bit/stage pipeline ADCs

Periodic signal digital testing

Reduced code linearity testing of pipeline adcs in the presence of noise