A nonvolatile memory (“NVM”) bitcell with one or more active regions capacitively coupled to the floating gate but that are separated from both the source and the drain. The inclusion of capacitors separated from the source and drain allows for improved control over the voltage of the floating gate. This in turn allows CHEI (or IHEI) to be performed with much higher efficiency than in existing bitcells, thereby the need for a charge pump to provide current to the bitcell, ultimately decreasing the total size of the bitcell. The bitcells may be constructed in pairs, further reducing the space requirements of the each bitcell, thereby mitigating the space requirements of the separate capacitor/s. The bitcell may also be operated by CHEI (or IHEI) and separately by BTBT depending upon the voltages applied at the source, drain, and capacitor/s.

Asymmetric dense floating gate nonvolatile memory with decoupled capacitor

A new two-transistor embedded resistive RAM (RRAM) cell with fully Taiwan Semiconductor Manufacturing Company 28-nm CMOS logic compatible process is reported. The new 28-nm logic compatible RRAM cell consists of two logic standard high- k metal gate (HKMG) CMOS transistors with a composite resistive gate dielectric of TiN/ HfO2/SiO2/Si as a resistive memory storage node. Using one of the transistor gates as a source line in RRAM SET/RESET operation, the resistive memory states can be efficiently read and sensed by selecting the other transistor gate and its corresponding bitline. Therefore, the new 2T embedded RRAM cell has realized a logic nonvolatile memory (NVM) solution with cost effective, and fully compatible with 28-nm HKMG CMOS logic platforms. Besides, through adapting the existing high- K gate dielectric in the RRAM cell, the embedded memory cell does not need any additional deposition of resistive film or extra process steps and it will be very scalable and compatible with the fast progress of CMOS technologies in embedded NVM applications. Furthermore, its low voltage requirement makes this cell conveniently fit in logic intellectual properties and circuits for local data storages or level trimming devices on system-on-chip logic NVM products.

28-nm 2T High- $K$ Metal Gate Embedded RRAM With Fully Compatible CMOS Logic Processes

A novel multiple-time programmable (MTP) single-poly EEPROM cell based on a half-MOS device is presented. The proposed cell is fabricated in a standard complementary metal-oxide-semiconductor (CMOS) process without any additional mask or process step. It is based on a novel approach, which provides many advantages with respect to the state-of-the-art standard MTP cells, in terms of area, program/erase performance, and endurance. A test-chip is fabricated in a standard 0.13 μm CMOS process and extensive experimental results are provided.

Half-MOS Single-Poly EEPROM Cell in Standard CMOS Process

A new fully logic process compatible 2T multitime programmable (MTP) memory cell has been introduced for embedded logic nonvolatile memory (NVM) applications. The cell adopts a novel contact coupling gate structure as an additional control gate for highly efficient operation and high-density memory applications. A new 2T n-channel MTP 2-Kb memory test chip has been also successfully demonstrated on pure 0.18- CMOS logic process without extra masking or process step. Furthermore, the embedded 2T MTP cell performs an efficiently program/erase operation by CHE injection and FN tunnel with highly reliable endurance and retention characteristics.

A New 2T Contact Coupling Gate MTP Memory in Fully CMOS Compatible Process

A new single-poly-EEPROM cell compatible with standard CMOS processes is proposed. A pMOS tunneling device is used for programming and erasing, and an nMOS transistor is used for reading and selecting the memory cell when it is in an array. The pMOS device is a minimum-sized digital transistor with the gate oxide of the input/output transistors. This improves the coupling capacitance, minimizes the area consumption, and guarantees the retention. The memory cell is programmed by band-to-band hot electrons and erased by Fowler–Nordheim tunneling. Thanks to the proposed writing scheme, the memory cell requires only a single triple-well. This further reduces the area consumption, and ensures, at the same time, fast and reliable memory operations. The measurements on programming, erasing, reading, cycling endurance, and data retention are provided using a 0.18- $\mu \text{m}$ standard CMOS process. The memory cell area is 5.91 $\mu \text{m}^{2}\vphantom {\sum ^{R^{r}}}$ in an array, and it can be programmed in $t_{P}=1$ ms, erased in $t_{E}=10$ ms, and cycled for >10k times with a voltage window greater than 2 V.

Single-Poly-EEPROM Cell in Standard CMOS Process for Medium-Density Applications

In this letter, we propose a new fully logic-process-compatible multitime programmable (MTP) memory cell for high-density logic nonvolatile memory (NVM) applications. A very small logic NVM MTP cell has been demonstrated on pure 0.18-μm CMOS process and logic design rules without extra masking and process steps. The MTP cell can be efficiently programmed and erased with a novel tiny contact coupling structure. Very small cell size, fast programming speed, and superior reliability characteristic make the new contact coupling gate MTP cell be one of the most promising solutions in advanced logic NVM application.

Haw-Yun Wu

Papers

A New 2T Contact Coupling Gate MTP Memory in Fully CMOS Compatible Process

A High-Density MTP Cell With Contact Coupling Gates by Pure CMOS Logic Process