Power dissipation and thermal issues are increasingly significant in modern processors. As a result, it is crucial that power/performance tradeoffs be made more visible to chip architects and even compiler writers, in addition to circuit designers. Most existing power analysis tools achieve high accuracy by calculating power estimates for designs only after layout or floorplanning are complete. In addition to being available only late in the design process, such tools are often quite slow, which compounds the difficulty of running them for a large space of design possibilities.This paper presents Wattch, a framework for analyzing and optimizing microprocessor power dissipation at the architecture-level. Wattch is 1000X or more faster than existing layout-level power tools, and yet maintains accuracy within 10% of their estimates as verified using industry tools on leading-edge designs. This paper presents several validations of Wattch's accuracy. In addition, we present three examples that demonstrate how architects or compiler writers might use Wattch to evaluate power consumption in their design process.We see Wattch as a complement to existing lower-level tools; it allows architects to explore and cull the design space early on, using faster, higher-level tools. It also opens up the field of power-efficient computing to a wider range of researchers by providing a power evaluation methodology within the portable and familiar SimpleScalar framework.

Wattch: a framework for architectural-level power analysis and optimizations

With power density and hence cooling costs rising exponentially, processor packaging can no longer be designed for the worst case, and there is an urgent need for runtime processor-level techniques that can regulate operating temperature when the package's capacity is exceeded. Evaluating such techniques, however, requires a thermal model that is practical for architectural studies.This paper describes HotSpot, an accurate yet fast model based on an equivalent circuit of thermal resistances and capacitances that correspond to microarchitecture blocks and essential aspects of the thermal package. Validation was performed using finite-element simulation. The paper also introduces several effective methods for dynamic thermal management (DTM): "temperature-tracking" frequency scaling, localized toggling, and migrating computation to spare hardware units. Modeling temperature at the microarchitecture level also shows that power metrics are poor predictors of temperature, and that sensor imprecision has a substantial impact on the performance of DTM.

Temperature-aware microarchitecture

A companion analysis of clock jitter and phase noise of single-ended and differential ring oscillators is presented. The impulse sensitivity functions are used to derive expressions for the jitter and phase noise of ring oscillators. The effect of the number of stages, power dissipation, frequency of oscillation, and short-channel effects on the jitter and phase noise of ring oscillators is analyzed. Jitter and phase noise due to substrate and supply noise is discussed, and the effect of symmetry on the upconversion of 1/f noise is demonstrated. Several new design insights are given for low jitter/phase-noise design. Good agreement between theory and measurements is observed.

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Jitter and phase noise in ring oscillators

With the increasing clock rate and transistor count of today's microprocessors, power dissipation is becoming a critical component of system design complexity. Thermal and power-delivery issues are becoming especially critical for high-performance computing systems. In this work, we investigate dynamic thermal management as a technique to control CPU power dissipation. With the increasing usage of clock gating techniques, the average power dissipation typically seen by common applications is becoming much less than the chip's rated maximum power dissipation. However system designers still must design thermal heat sinks to withstand the worse-case scenario. We define and investigate the major components of any dynamic thermal management scheme. Specifically we explore the tradeoffs between several mechanisms for responding to periods of thermal trauma and we consider the effects of hardware and software implementations. With approximate dynamic thermal management, the CPU can be designed for a much lower maximum power rating, with minimal performance impact for typical applications.

Dynamic thermal management for high-performance microprocessors

With cooling costs rising exponentially, designing cooling solutions for worst-case power dissipation is prohibitively expensive. Chips that can autonomously modify their execution and power-dissipation characteristics permit the use of lower-cost cooling solutions while still guaranteeing safe temperature regulation. Evaluating techniques for this dynamic thermal management (DTM), however, requires a thermal model that is practical for architectural studies.This paper describes HotSpot, an accurate yet fast and practical model based on an equivalent circuit of thermal resistances and capacitances that correspond to microarchitecture blocks and essential aspects of the thermal package. Validation was performed using finite-element simulation. The paper also introduces several effective methods for DTM: "temperature-tracking" frequency scaling, "migrating computation" to spare hardware units, and a "hybrid" policy that combines fetch gating with dynamic voltage scaling. The latter two achieve their performance advantage by exploiting instruction-level parallelism, showing the importance of microarchitecture research in helping control the growth of cooling costs.Modeling temperature at the microarchitecture level also shows that power metrics are poor predictors of temperature, that sensor imprecision has a substantial impact on the performance of DTM, and that the inclusion of lateral resistances for thermal diffusion is important for accuracy.

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Temperature-aware microarchitecture: Modeling and implementation

A 28 mW/MHz at 80 MHz structured-custom RISC microprocessor design is described. This 32-b implementation of the PowerPC architecture is fabricated in a 3.3 V, 0.5 /spl mu/m, 4-level metal CMOS technology, resulting in 1.6 million transistors in a 7.4 mm by 11.5 mm chip size. Dual 8-kilobyte instruction and data caches coupled to a high performance 32/64-b system bus and separate execution units (float, integer, loadstore, and system units) result in peak instruction rates of three instructions per clock cycle. Low-power design techniques are used throughout the entire design, including dynamically powered down execution units. Typical power dissipation is kept under 2.2 W at 80 MHz. Three distinct levels of software-programmable, static, low-power operation-for system power management are offered, resulting in standby power dissipation from 2 mW to 350 mW. CPU to bus clock ratios of 1/spl times/, 2/spl times/, 3/spl times/, and 4/spl times/ are implemented to allow control of system power while maintaining processor performance. As a result, workstation level performance is packed into a low-power, low-cost design ideal for notebooks and desktop computers. >

A 2.2 W, 80 MHz superscalar RISC microprocessor

Thermal management is an important design issue in high-performance, low-power portable computers If the computer system is designed for worst-case processor power dissipation and environmental operating conditions, it carries an area and cost penalty for the system designer The next-generation PowerPC/sup TM/ microprocessor includes a thermal assist unit (TAU) comprised of an on-chip thermal sensor and associated logic The TAU monitors the junction temperature of the processor and dynamically adjusts processor operation to provide maximum performance under changing environmental conditions The TAU is used in conjunction with other low-power features such as dynamic power management, instruction cache throttling and static low-power modes to provide comprehensive power and thermal management This paper describes the implementation of the TAU and presents its characterization and operating data from first silicon

Thermal management system for high performance PowerPC/sup TM/ microprocessors

A 3.3 V Phase-Locked-Loop (PLL) clock synthesizer implemented in 0.5 /spl mu/m CMOS technology is described. The PLL supports internal to external clock frequency ratios of 1, 1.5, 2, 3, and 4 as well as numerous static power down modes for PowerPC microprocessors. The CPU clock lock range spans from 6 to 175 MHz. Lock times below 15 /spl mu/s, PLL power dissipation below 10 mW as well as phase error and jitter below /spl plusmn/100 ps have been measured. The total area of the PLL is 0.52 mm/sup 2/. >

A wide-bandwidth low-voltage PLL for PowerPC microprocessors

A Wide-Bandwidth Low-Voltage PLL for PowerPC TM Microprocessors

The continued scaling of transistor performance is delivering unprecedented microprocessor performance. However, the logic supply voltage, Vdd, is being reduced at a faster rate than the required I/O voltage level, OVDD. OVDD scales more slowly due to peripherals, which are built on mature technologies that require higher OVDD. Time-to-market constraints and chip integration issues further impose a single I/O driver as the desired solution. The I/O driver must meet the reliability constraints of the 3.3 V interface with a transistor that has a 3.5 nm Tox (no dual-gate oxide processing step). The 128b L2 interface must run at 400MHz clock rate and the 128b system interface at 150MHz. Both interfaces are compatible with the 3.3V/2.5V interfaces ofthe PowerPC TM 750, yet support more aggressive 1.8V systems.

Hector Sanchez

Papers

A 2.2 W, 80 MHz superscalar RISC microprocessor

Thermal management system for high performance PowerPC/sup TM/ microprocessors

A wide-bandwidth low-voltage PLL for PowerPC microprocessors

A Wide-Bandwidth Low-Voltage PLL for PowerPC TM Microprocessors

A versatile 3.3 V/2.5 V/1.8 V CMOS I/O driver built in a 0.2 /spl mu/m 3.5 nm Tox 1.8 V CMOS technology