Showing papers by "Heng-Yuan Lee published in 2018"

Extremely Steep Switch of Negative-Capacitance Nanosheet GAA-FETs and FinFETs

Abstract: Extremely steep switch of negative-capacitance (NC) Nanosheet (NS) GAA-FETs and FinFETs are experimentally presented with $\text{SS}_{\text{avg}}/\text{SS}_{\min}=22/14\text{mV}/\text{dec}$ and $\text{SS}_{\text{avg}}/\text{SS}_{\min}=38/21\ \text{mV}/\text{dec}$ , respectively. The sub-60m V/dec current magnitude of sub-60mV/dec is >4 and ∼5 decades for NC-NSGAA and NC-FinFET, respectively. Both NC-NSGAA and NC-FinFET exhibit extremely steep switch behavior due to FET scale down to nano-scale and comparable domain size of polycrystalline HZO. The dramatic current switch with steep slope is measured with only several dipole domains flipping over with gate voltage applied. The apparent Negative-DIBL and NDR (Negative Differential Resistance) are observed due to strong NC boost. The SS depends on WFin/L ratio, and $\mathrm{W}_{\text{Fin}} is the solution to achieve sub-60m V/dec. The super-steep slope on current behavior still occurs after multiple DC sweep. The uniform size of each NS for stacked NC-NSGAA is an important issue to optimize the NC effect with $\text{SS} =19\text{mV}/\text{dec}$ due to single T NS for capacitance matching by modeling.

Highly Reliable Two-Step Charge-Pump Read Scheme for 1.5 F 2 /Bit Nonlinear Sub-Teraohm 0TNR Vertical ReRAM

Abstract: Among the emerging types of memory, resistive random-access memory (ReRAM) units offer faster write speeds and consume less power than those of flash memory units. With the advancement of 3-D stack technology, 3-D nonvolatile memories (NVMs) are under active development to satisfy the requirements of new applications. This brief proposes a 1.5 F2/bit nonlinear sub-teraohm vertical ReRAM (V-ReRAM) and a sensing ultrahigh-resistance read scheme that not only accurately senses sub-picoampere currents but also reduces sneak current effects. A 2-Kb V-ReRAM macro unit was fabricated using a 0.15- $\mu \text{m}$ CMOS process and the Industrial Technology Research Institute’s zero-transistor-four-ReRAM V-ReRAM back-end-of-line process. The proposed read scheme increased the sensing margin by eight times when compared with the current-mirror type, a commonly used read scheme for NVMs. Additionally, the memory bit size was smaller than one-transistor-N-ReRAM V-ReRAM.