Henry Hoffman

TL;DR: The Raw microprocessor research prototype uses a scalable instruction set architecture to attack the emerging wire-delay problem by providing a parallel, software interface to the gate, wire and pin resources of the chip.

TL;DR: The 0.15/spl mu/m 6M microprocessor as mentioned in this paper uses 16 unique instructions per cycle and uses an on-chip point-to-point scalar operand network to transfer operands among distributed functional units.

TL;DR: This microprocessor explores an architectural solution to scalability problems in scalar operand networks by using an on-chip point-to-point scalaroperand network to transfer operands among distributed functional units.

TL;DR: ATAC, a new manycore architecture that capitalizes on the recent advances in optics to address a number of challenges that future manycore designs will face, is introduced and Consumer Tagging is introduced, a novel programming model that leverages ATAC's strengths to provide high performance and scalability.

TL;DR: This thesis describes the SEEC framework and evaluates it in several case studies, demonstrating that SEEC can have a positive impact on real systems by understanding high level goals and adapting to meet those goals online.