Jason E. Miller

TL;DR: This paper introduces the Graphite open-source distributed parallel multicore simulator infrastructure and demonstrates that Graphite can simulate target architectures containing over 1000 cores on ten 8-core servers with near linear speedup.

TL;DR: The evaluation attempts to determine the extent to which Raw succeeds in meeting its goal of serving as a more versatile, general-purpose processor, and proposes a new versatility metric that uses it to discuss the generality of Raw.

TL;DR: ATAC, a new multicore architecture with integrated optics, and ACKwise, a novel cache coherence protocol designed to leverage ATAC's strengths are presented, showing that ATAC withACKwise out-performs a chip with conventional interconnect and cache coherent protocols.

TL;DR: The Applications Heartbeats interface provides a standard method for an application to directly communicate its performance and goals while allowing autonomic services access to this information, and Heartbeat-enabled applications are no longer performance black-boxes.

TL;DR: The 0.15/spl mu/m 6M microprocessor as mentioned in this paper uses 16 unique instructions per cycle and uses an on-chip point-to-point scalar operand network to transfer operands among distributed functional units.