A predictive MOSFET model is critical for early circuit design research. To accurately predict the characteristics of nanoscale CMOS, emerging physical effects, such as process variations and correlations among model parameters, must be included. In this paper, a new generation of predictive technology model (PTM) is developed to accomplish this goal. Based on physical models and early-stage silicon data, the PTM of bulk CMOS is successfully generated for 130- to 32-nm technology nodes, with an Leff of as low as 13 nm. The accuracy of PTM predictions is comprehensively verified: The error of I on is below 10% for both n-channel MOS and p-channel MOS. By tuning only ten primary parameters, the PTM can be easily customized to cover a wide range of process uncertainties. Furthermore, the new PTM correctly captures process sensitivities in the nanometer regime, particularly the interactions among Leff, Vth, mobility, and saturation velocity. A website has been established for the release of PTM: http://www.eas.asu.edu/~ptm

New Generation of Predictive Technology Model for Sub-45 nm Early Design Exploration

Predictive MOSFET model is critical for early circuit design research. To accurately predict the characteristics of nanoscale CMOS, emerging physical effects, such as process variations and physical correlations among model parameters, must be included. In addition, predictions across technology generations should be smooth to make continuous extrapolations. In this work, a new generation of predictive technology model (PTM) is developed to accomplish these goals. Based on physical models and early stage silicon data, PTM of bulk CMOS for 130nm to 32nm technology nodes is successfully generated. By tuning ten parameters, PTM can be easily customized to cover a wide range of process uncertainties. The accuracy of PTM predictions is comprehensively verified: for NMOS, the error of I/sub on/ is 2% and for PMOS, it is 5%. Furthermore, the new PTM correctly captures process sensitivities in the nanometer regime. A webpage has been established for the release of PTM (http://www.eas.asu.edu//spl sim/ptm).

New Generation of Predictive Technology Model for Sub-45nm Design Exploration

A predictive MOSFET model is critical for early circuit design research. In this work, a new generation of Predictive Technology Model (PTM) is developed, covering emerging physical effects and alternative structures, such as the double-gate device (i.e., FinFET). Based on physical models and early stage silicon data, PTM of bulk and double-gate devices are successfully generated from 130nm to 32nm technology nodes, with effective channel length down to 13nm. By tuning only ten primary parameters, PTM can be easily customized to cover a wide range of process uncertainties. The accuracy of PTM predictions is comprehensively verified with published silicon data: the error of the current is below 10p for both NMOS and PMOS. Furthermore, the new PTM correctly captures process sensitivities in the nanometer regime. PTM is available online at http://www.eas.asu.edu/~ptm.

Predictive technology model for nano-CMOS design exploration

Subthreshold logic is an efficient technique to achieve ultralow energy per operation for low-to-medium throughput applications. In this paper, the interests and limitations of technology scaling for subthreshold logic are investigated from 0.25 mum to 32 nm nodes. Scaling to 90/65 nm nodes is shown to be highly desirable for medium-throughput applications (1-10 MHz) due to great dynamic energy reduction. However, this interest is limited at 45/32 nm nodes by high static energy due to degraded subthreshold swing and delay variability. Moreover, for low-throughput applications (10-100 kHz), this limitation is worsened by the increase of minimum supply voltage to achieve sufficient functional yield, which results in bad energy efficiency starting at 0.13 mum node. Upsizing the channel length is proposed as a straightforward circuit-level technique to efficiently mitigate these effects. At 32 nm node, this technique reduces energy per operation by 60% at medium throughput and by two orders of magnitude at low throughput.

Interests and Limitations of Technology Scaling for Subthreshold Logic

Nanowire (NW) devices, particularly the gate-all-around (GAA) CMOS architecture, have emerged as the front-runner for pushing CMOS scaling beyond the roadmap. These devices offer unique advantages over their planar counterparts which make them feasible as an option for 22 -nm and beyond technology nodes. This paper reviews the current technology status for realizing the GAA NW device structures and their applications in logic circuit and nonvolatile memories. We also take a glimpse into applications of NWs in the ldquomore-than-Moorerdquo regime and briefly discuss the application of NWs as biochemical sensors. Finally, we summarize the status and outline the challenges and opportunities of the NW technology.

Si, SiGe Nanowire Devices by Top–Down Technology and Their Applications

Aggressively scaled 30 nm gate CMOSFETs for 45 nm node is reported We successfully improved the short channel effect with keeping a high drive current by Sigma shaped SiGe-source/drain (SiGe-SD) structure Both hole mobility and source/drain extension (SDE) resistance in pMOSFET are improved by combination of optimized Sigma shaped SiGe-SD and slit-embedded B-doped SiGe-SDE Electron and hole mobility enhancement can be balanced by aggressively scaled poly-Si pMOS gate height and SiN capped shallow trench isolation (STI) with SiN liner A high performance 30 nm/33 nm gate nMOSFET and pMOSFET were demonstrated with a drive currents of 937/1000 muA/mum and 490/545 muA/mum at Vd=10 V / Ioff=100 nA/mum, respectively

High performance 30 nm gate bulk CMOS for 45 nm node with /spl Sigma/-shaped SiGe-SD

A semiconductor device manufacture method includes the steps of forming a resist layer above a work target layer; exposing and developing the resist layer to form resist patterns including isolated pattern and dense patterns; monitoring widths of isolated and dense pattern of the resist patterns to determine trimming amounts of linewidths to be reduced; determining etching conditions for realizing the trimming amounts of both the isolated and dense patterns, the etching conditions using mixed gas of a gas having a function of mainly enhancing etching and a gas having a function of mainly suppressing etching; trimming the resist pattern under said determined etching conditions; and etching the work target layer by using said trimmed resist patterns. A desired pattern width an be realized stably by trimming using plasma etching.

Semiconductor device manufacture method and etching system

A new powerful strain booster named as dopant confinement layer (DCL) technique is proposed for the first time. DCL technique is a novel stress memorization technique (SMT). Our proposed method doesn't require any additional capping layers used in SMT. DCL fabricated directly on the gate dielectric film effectively improved drive currents without degrading short channel immunity because DCL technique dose not affect halo, extension and source/drain (S/D) profiles. The higher dopant concentration in DCL resulted in both the better electron mobility and the thinner equivalent oxide thickness of inversion layer capacitance (Teff). Consequently, the higher drive currents of 1204 muA/mum and 786 muA/mum were obtained at Vdd=1.0 V for nMOSFET and pMOSFET, respectively.

High Performance Sub-40 nm Bulk CMOS with Dopant Confinement Layer (DCL) technique as a Strain Booster

A method of manufacturing a semiconductor device has forming a first silicon film over the first insulating film, forming a second film over the first silicon film, a first etching the second silicon film in a depth, which that first silicon film is not exposed, in first condition, on a second etching a remaining portion of the second silicon film and the first silicon film in a depth, which the first insulating film is not exposed, in second condition which gives a higher vertical etching component ratio that the first condition; and a third etching a remaining portion of the first silicon film in third condition which an etching rate for the first silicon film is larger than an etching rate for the first insulating film as compared to the second condition, wherein in impurity concentration of a first conductivity type of the first silicon film is higher than an impurity concentration of the first conductivity type of the second silicon film.

Semiconductor device and method of manufacturing the same

A semiconductor device includes a transistor configuration including first and second gate electrodes, each of the first and second gate electrodes having at least a bottom layer and an upper layer including polycrystalline silicon grains, wherein the first gate electrode is a nMOS gate electrode formed in an nMOS region of the transistor configuration, wherein the polycrystalline silicon grains included in the bottom layer of the first gate electrode have a greater particle diameter than the polycrystalline grains included in the upper layer of the second gate electrode.

M. Tajima

Papers

High performance 30 nm gate bulk CMOS for 45 nm node with /spl Sigma/-shaped SiGe-SD

Semiconductor device manufacture method and etching system

High Performance Sub-40 nm Bulk CMOS with Dopant Confinement Layer (DCL) technique as a Strain Booster

Semiconductor device and method of manufacturing the same

Semiconductor device and method of manufacturing the semiconductor device