Maximum baud rate of electrical signaling over backplanes is limited by reflection and crosstalk noise at connectors as well as ISI caused by frequency-dependent dielectric loss. A DFE is an effective circuit to alleviate ISI without amplifying noise. A multi-tap DFE is often used in order to cancel long-tail ISI [1–3]. However, multiple DFE taps may limit maximum operation speed due to analog feedback when using non-speculative taps [1,2], or increase power and area exponentially when using multiple speculative taps [3]. Another approach is a combination of a 1-tap speculative DFE to get faster speed and a linear equalizer (LE) to cancel the long-tail ISI [4,5]. Adaptive control is challenging when combining LE and DFE, because the relationship between LE and DFE must be taken into account [5], and the sign-sign-least-mean-square (SS-LMS) algorithm [7] that is commonly used in DFEs is not applicable to some types of LE, or at the cost of increased power and area for parallel signal paths in LE [6]. The zero-forcing (ZF) algorithm for analog filters [8] is applicable to any type of LE, but it needs an ADC and a large amount of logic to perform matrix multiplication. A heuristic algorithm [5] requires an eye measurement circuit, microcontroller, and control software.

A 4-Channel 1.25–10.3 Gb/s Backplane Transceiver Macro With 35 dB Equalizer and Sign-Based Zero-Forcing Adaptive Control

A 12.3-mW 12.5-Gb/s complete transceiver based on the 65-nm standard digital CMOS process was developed. The chip includes a clock-and-data-recovery (CDR) device, a multiplexer/demultiplexer (MUX/DEMUX), and a global clock-distribution network. To reduce power consumption, a low-swing voltage-mode driver with pulse-current boosting and an LC resonant-clock distribution with distributed on-chip inductors are used in the transmitter, while a symbol-rate phase detector (SPD) using a three-stage sense amplifier and phase-rotating phase-locked loop (PLL) with variable delay are used in the receiver. The transceiver operates at a bit error rate (BER) of 10-12 or less through a 20-cm test board with total attenuation of -12.1 dB while consuming power of 0.98 mW/(Gb/s) per transceiver.

A 12.3-mW 12.5-Gb/s Complete Transceiver in 65-nm CMOS Process

This paper presents a quarter-rate clock and data recovery (CDR) circuit for plesiochronous serial I/O-links. The 2times-oversampling phase-tracking CDR, implemented in 90 nm bulk CMOS technology, covers the whole range of data rates from 5.75 to 44 Gb/s realized in a single IC by the novel feature of a data rate selection logic. Input data are sampled with eight parallel differential master-slave flip-flops, where bandwidth enhancement techniques were necessary for 90 nm CMOS. Precise and low-jitter local clock phases are generated by an analog delay-locked loop. These clock phases are aligned to the incoming data by four parallel phase rotators. The phase-tracking loop of the CDR is realized as a digital delay-locked loop and is therefore immune against process tolerances. The CDR is able to track a maximum frequency deviation of plusmn615 ppm between incoming data and a local reference clock and fulfills the extended XAUI jitter tolerance mask. A bit error rate <10-12 was verified up to 38 Gb/s using a 27 -1 PRBS pattern. With a low power consumption per data rate of only 5.74 mW/(Gb/s) the CDR meets the specifications of the International Technology Roadmap for Semiconductors for 90 nm CMOS serial I/O-links at the maximal data rate of 44 Gb/s. The CDR occupies a chip area of 0.2 mm2.

A 5.75 to 44 Gb/s Quarter Rate CDR With Data Rate Selection in 90 nm Bulk CMOS

This paper presents a 1.5 to 10 Gb/s SATA/SAS/FC receiver in 65 nm CMOS. The multiple constraints set by industry standards ask for a receiver architecture capable of simultaneously addressing channel loss impairments, high frequency-difference tracking and low serial to parallel latency. An adaptive 3-tap DFE data recovery is based on a direct-feedback topology to provide a continuous equalized signal assuring a robust clock-data self alignment. A latch-based DFE topology has been developed to overcome the classical DFE feedback loop-delay issue. A digital early-late clock recovery has been proven for plusmn5000 ppm SSC tracking. Extensive digital features allow self-calibration and internal eye analysis. The device, realized in a 65 nm technology, supports more than 36" FR4 at 6 Gb/s with SSC and 28" at 8.5 Gb/s while keeping 0.4 UI of additional sinusoidal jitter tolerance, consuming 140 mW from 1V.

A Multi-Standard 1.5 to 10 Gb/s Latch-Based 3-Tap DFE Receiver With a SSC Tolerant CDR for Serial Backplane Communication

This paper describes an ultralow-power VCSEL transmitter in 32 nm SOI CMOS. To increase its power efficiency, the VCSEL is driven at a low bias current. Driving the VCSEL in this condition increases its inherent nonlinearity. Conventional pre-emphasis techniques cannot compensate for this effect because they have a linear response. To overcome this limitation, a nonlinear equalization scheme is proposed. A dynamic VCSEL modelling technique is used to generate the time-domain optical responses for “one” and “zero” bits. Based on the asymmetry of the two responses, the rising and falling edges are equalized separately. Additionally, instead of using fixed bit delays, the equalization delay is selected based on the bias current of the VCSEL. The efficiency of the proposed modelling and equalization technique is evaluated through simulations and measurements. The transmitter achieves energy efficiency of 0.77 pJ/b at 20 Gb/s and occupies $100\ \upmu\text{m} \times 60\ \upmu\text{m}$ active silicon area.

A Modelling and Nonlinear Equalization Technique for a 20 Gb/s 0.77 pJ/b VCSEL Transmitter in 32 nm SOI CMOS

IT systems such as servers and routers need high-speed lower- power area-efficient chip-to-chip interconnections through backplane boards. These interconnections must overcome signal degradation due to the large insertion loss of low-cost boards. In this work, a 90nm CMOS 8Gb/s transceiver is developed. A TX 5- tap FFE, an RX analog equalizer, and a 2-tap DFE combined with a 2-threshold eye-tracking CDR achieve a BER of less than 10-12 through a 160cm backplane board with -36.8dB loss at 4GHz and a transceiver power consumption of 232mW (transmission efficiency of 1.2Gb/sxdB/mW).

An 8Gb/s Transceiver with 3×-Oversampling 2-Threshold Eye-Tracking CDR Circuit for -36.8dB-loss Backplane

This paper describes the design and experimental results of a 4 × 10 Gb/s vertical-cavity surface-emitting laser (VCSEL) driver using the asymmetric emphasis technique. Conventional symmetric emphasis techniques can compensate for the influences of parasitic capacitances; however, they cannot compensate for the nonlinear effects of a VCSEL. To overcome this problem, an asymmetric emphasis technique that can separately control the emphasis pulses at the rising and falling edges is proposed. This allows fast transition in VCSEL output waveform suppressing ringing. A driver circuit that has two separate emphasis circuits for the rising and falling edges is proposed in order to implement the asymmetric emphasis technique. This configuration enables us to separately control the height, width, and setup time of the emphasis pulses at the rising and falling edges. The test chip fabricated by using 90-nm CMOS technology generates a clearly open optical eye at a data rate of 10 Gb/s, and we can confirm the existence of a wide phase margin by a transmission experiment.

Design of a 4 $\times$ 10 Gb/s VCSEL Driver Using Asymmetric Emphasis Technique in 90-nm CMOS for Optical Interconnection

In an environment in which signal-to-noise is poor, a method and a system configuration for power-saving, low-cost, and general minute signal detection are provided. The system includes a circuit that converts and amplifies an input signal, a nonlinear analog front-end circuit that determines the existence of a minute signal from the input signal and that outputs information on the existence of the same as an event signal, an analog-to-digital-conversion circuit that drives operation-mode control based on the event signal and performs analog-to-digital conversion on the converted-and-amplified input signal, a data-transfer circuit that drives the operation-mode control by the event signal and transfers the analog-to-digital converted signal, a digital-signal-processing circuit that drives the operation-mode control by the event signal and performs digital-signal processing on the signal transmitted from the data-transfer circuit and detects the signal, and a parameter-control circuit that controls a characteristic parameter of the nonlinear analog front-end circuit.

Minute Signal Detection Method and System

One of a group which is located on the side of a main surface of the circuit board than the one conductive layer of the plurality of conductive layers is used as a terminal to detect the digging depth of the through hole, and the digging of the through hole is stopped according to the change of the conductive state between the detection terminal and the through hole (or the one conductive layer which is electrically connected to this). A circuit board is formed so that the detection terminal in a group of the plurality of conductive layers contacts with the drill which dig the through hole and a group of the conductive layers except the detection terminal does not contact with the drill, respectively.

Circuit board provided and transmission device with the same mounted

Provided is a device operation status identification device and method with which it is possible to automatically and accurately distinguish between device operation statuses at low cost under low network load. The invention is provided with a data acquisition unit for acquiring data relating to the device operation status, a feature amount extraction unit for extracting feature amounts on the basis of the data acquired by the data acquisition unit, a clustering unit for classifying the feature amounts extracted by the feature amount extraction unit to create clusters, a labeled-data creating unit for creating data in which the feature amounts classified by the clustering unit are labeled with the clustered device operation statuses to which the classified feature amounts belong, a memory unit for storing the data created by the labeled-data creating unit, and a status determining unit for determining the device operation status on the basis of the feature amounts extracted by the feature amount extraction unit and the data stored in the memory unit and outputting the determination results.

Hisaaki Kanai

Papers

An 8Gb/s Transceiver with 3×-Oversampling 2-Threshold Eye-Tracking CDR Circuit for -36.8dB-loss Backplane

Design of a 4 $\times$ 10 Gb/s VCSEL Driver Using Asymmetric Emphasis Technique in 90-nm CMOS for Optical Interconnection

Minute Signal Detection Method and System

Circuit board provided and transmission device with the same mounted

Facility management device and method