This article introduces McPAT, an integrated power, area, and timing modeling framework that supports comprehensive design space exploration for multicore and manycore processor configurations ranging from 90nm to 22nm and beyond. At microarchitectural level, McPAT includes models for the fundamental components of a complete chip multiprocessor, including in-order and out-of-order processor cores, networks-on-chip, shared caches, and integrated system components such as memory controllers and Ethernet controllers. At circuit level, McPAT supports detailed modeling of critical-path timing, area, and power. At technology level, McPAT models timing, area, and power for the device types forecast in the ITRS roadmap. McPAT has a flexible XML interface to facilitate its use with many performance simulators.Combined with a performance simulator, McPAT enables architects to accurately quantify the cost of new ideas and assess trade-offs of different architectures using new metrics such as Energy-Delay-Area2 Product (EDA2P) and Energy-Delay-Area Product (EDAP). This article explores the interconnect options of future manycore processors by varying the degree of clustering over generations of process technologies. Clustering will bring interesting trade-offs between area and performance because the interconnects needed to group cores into clusters incur area overhead, but many applications can make good use of them due to synergies from cache sharing. Combining power, area, and timing results of McPAT with performance simulation of PARSEC benchmarks for manycore designs at the 22nm technology shows that 8-core clustering gives the best energy-delay product, whereas when die area is taken into account, 4-core clustering gives the best EDA2P and EDAP.

https://dl.acm.org/doi/pdf/10.1145/2445572.2445577

The McPAT Framework for Multicore and Manycore Architectures: Simultaneously Modeling Power, Area, and Timing

System-in-Package (SiP) and 3D integration are promising technologies to bring more memory onto a microprocessor package to mitigate the "memory wall" problem. In this paper, instead of using them to build caches, we study a heterogenous main memory using both on- and off-package memories providing both fast and high-bandwidth on-package accesses and expandable and low-cost commodity off-package memory capacity. We introduce another layer of address translation coupled with an on-chip memory controller that can dynamically migrate data between off-package and off-package memory either in hardware or with operating system assistance depending on the migration granularity. Our experimental results demonstrate that such design can achieve the average effectiveness of 83% of the ideal case where all memory can be placed in high-speed on-package memory for our simulated benchmarks.

Simple but Effective Heterogeneous Main Memory with On-Chip Memory Controller Support

Memory bandwidth has been one of the most critical system performance bottlenecks. As a result, the HMC (Hybrid Memory Cube) has recently been proposed to improve DRAM bandwidth as well as energy efficiency. In this paper, we explore different system interconnect designs with HMCs. We show that processor-centric network architectures cannot fully utilize processor bandwidth across different traffic patterns. Thus, we propose a memory-centric network in which all processor channels are connected to HMCs and not to any other processors as all communication between processors goes through intermediate HMCs. Since there are multiple HMCs per processor, we propose a distributor-based network to reduce the network diameter and achieve lower latency while properly distributing the bandwidth across different routers and providing path diversity. Memory-centric networks lead to some challenges including higher processor-to-processor latency and the need to properly exploit the path diversity. We propose a pass-through microarchitecture, which, in combination with the proper intra-HMC organization, reduces the zero-load latency while exploiting adaptive (and non-minimal) routing to load-balance across different channels. Our results show that memory-centric networks can efficiently utilize processor bandwidth for different traffic patterns and achieve higher performance by providing higher memory bandwidth and lower latency.

Memory-centric system interconnect design with hybrid memory cubes

The performance of future manycore processors will only scale with the number of integrated cores if there is a corresponding increase in memory bandwidth. Projected scaling of electrical DRAM architectures appears unlikely to suffice, being constrained by processor and DRAM pin-bandwidth density and by total DRAM chip power, including off-chip signaling, cross-chip interconnect, and bank access energy. In this work, we redesign the DRAM main memory system using a proposed monolithically integrated silicon photonics technology and show that our photonically interconnected DRAM (PIDRAM) provides a promising solution to all of these issues. Photonics can provide high aggregate pin-bandwidth density through dense wavelength-division multiplexing. Photonic signaling provides energy-efficient communication, which we exploit to not only reduce chip-to-chip interconnect power but to also reduce cross-chip interconnect power by extending the photonic links deep into the actual PIDRAM chips. To complement these large improvements in interconnect bandwidth and power, we decrease the number of bits activated per bank to improve the energy efficiency of the PIDRAM banks themselves. Our most promising design point yields approximately a 10x power reduction for a single-chip PIDRAM channel with similar throughput and area as a projected future electrical-only DRAM. Finally, we propose optical power guiding as a new technique that allows a single PIDRAM chip design to be used efficiently in several multi-chip configurations that provide either increased aggregate capacity or bandwidth.

/pdf/re-architecting-dram-memory-systems-with-monolithically-pg7axlcn5p.pdf

Re-architecting DRAM memory systems with monolithically integrated silicon photonics

The twenty-first century has witnessed major technological changes that have transformed the way we live, work, and interact with one another. One of the major technology enablers responsible for this remarkable transformation in our global society is the deployment and use of Information and Communication Technology (ICT) equipment. In fact, today ICT has become highly integrated in our society that includes the dependence on ICT of various sectors, such as business, transportation, education, and the economy to the point that we now almost completely depend on it. Over the last few years, the energy consumption resulting from the usage of ICT equipment and its impact on the environment have fueled a lot of interests among researchers, designers, manufacturers, policy makers, and educators. We present some of the motivations driving the need for energy-efficient communications. We describe and discuss some of the recent techniques and solutions that have been proposed to minimize energy consumption by communication devices, protocols, networks, end-user systems, and data centers. In addition, we highlight a few emerging trends and we also identify some challenges that need to be addressed to enable novel, scalable, cost-effective energy-efficient communications in the future.

Energy-efficient networking: past, present, and future

A 12.3-mW 12.5-Gb/s complete transceiver based on the 65-nm standard digital CMOS process was developed. The chip includes a clock-and-data-recovery (CDR) device, a multiplexer/demultiplexer (MUX/DEMUX), and a global clock-distribution network. To reduce power consumption, a low-swing voltage-mode driver with pulse-current boosting and an LC resonant-clock distribution with distributed on-chip inductors are used in the transmitter, while a symbol-rate phase detector (SPD) using a three-stage sense amplifier and phase-rotating phase-locked loop (PLL) with variable delay are used in the receiver. The transceiver operates at a bit error rate (BER) of 10-12 or less through a 20-cm test board with total attenuation of -12.1 dB while consuming power of 0.98 mW/(Gb/s) per transceiver.

A 12.3-mW 12.5-Gb/s Complete Transceiver in 65-nm CMOS Process

For the people involved with multi-Gb/s chip-to-chip serial links, reducing power dissipation per Gb/s to less than 1mW/(Gb/s) (i.e., 1pJ/b) has been a long-held goal. Several years ago, the power dissipation of these links was in the range of about 10 to 20mW/(Gb/s). In 2007, Poulton et al. developed a 14mW 6.25Gb/s transceiver with power efficiency of 2.2mW/(Gb/s) [1]. Thereafter, there were some efforts aiming to reduce power of each building block in a transceiver [2, 3]. This paper presents a 12.3mW 12.5Gb/s complete transceiver (including CDR, MUX/DEMUX, and global clock distribution)in 65nm CMOS with power efficiency of 0.98mW/(Gb/s). To achieve low power, a resonant-clock distribution with distributed on-chip inductors and a low-swing voltage-mode driver with pulse-current boosting are used in the transmitter, while a symbol-rate comparator/phase detector using 4-stage sense amplifier and phase-rotating PLL with variable delay are used in the receiver.

A 12.3mW 12.5Gb/s complete transceiver in 65nm CMOS

The 100-gigabit Ethernet (100GbE) was standardized as IEEE 802.3ba in 2010 [1]. The optics module must be equipped with a “gearbox” LSI-which switches between 10×10Gb/s data signals on the physical-coding-sublayer side and 4×25Gb/s data signals on the physical-media-dependent side. A gearbox LSI based on 0.13 μm SiGe BiCMOS consumes 8W of power [2], which is about half of the total power consumption of the optics module. Aiming to reduce the power consumption, a 50Gb/s 2:5 DEMUX based on CMOS technology is developed [3]. In addition, since the architecture in reference [2] consists of two LSIs (MUX and DEMUX), loop-back operation, which is required in the IEEE standard, is impossible. In response to these circumstances, we have developed a 100GbE gearbox LSI combining a 10:4 MUX and a 4:10 DEMUX. This gearbox LSI — implemented in 65nm CMOS — decreases power dissipation by 75% compared to that of a conventional LSI.

A 10:4 MUX and 4:10 DEMUX Gearbox LSI for 100-Gigabit Ethernet Link

IT systems such as servers and routers need high-speed lower- power area-efficient chip-to-chip interconnections through backplane boards. These interconnections must overcome signal degradation due to the large insertion loss of low-cost boards. In this work, a 90nm CMOS 8Gb/s transceiver is developed. A TX 5- tap FFE, an RX analog equalizer, and a 2-tap DFE combined with a 2-threshold eye-tracking CDR achieve a BER of less than 10-12 through a 160cm backplane board with -36.8dB loss at 4GHz and a transceiver power consumption of 232mW (transmission efficiency of 1.2Gb/sxdB/mW).

An 8Gb/s Transceiver with 3×-Oversampling 2-Threshold Eye-Tracking CDR Circuit for -36.8dB-loss Backplane

The first CMOS "gearbox LSI" based on 65-nm CMOS technology—namely, a 2-W 100-Gigabit-Ethernet gearbox LSI combining a 10:4 multiplexer and a 4:10 demultiplexer—was developed. Its power dissipation is 75% lower than that of a conventional SiGe-based gearbox LSI. To develop this low-power gearbox LSI, the power dissipation of its 25-Gb/s interface is decreased to 14 mW/Gb/s by three circuit schemes: maximizing the use of CMOS circuits, adopting a low-power circuit archi- tecture for a current-mode-logic (CML) circuit, and minimizing clock distribution by using a flip-flop with a single-clock operation and a PLL with phase rotation for each channel. The 25-Gb/s interface in the LSI provides a transmitter output with sufficient eye opening and achieved minimum input sensitivity of 34.4-mV (peak-to-peak).

Koji Fukuda

Papers

A 12.3-mW 12.5-Gb/s Complete Transceiver in 65-nm CMOS Process

A 12.3mW 12.5Gb/s complete transceiver in 65nm CMOS

A 10:4 MUX and 4:10 DEMUX Gearbox LSI for 100-Gigabit Ethernet Link

An 8Gb/s Transceiver with 3×-Oversampling 2-Threshold Eye-Tracking CDR Circuit for -36.8dB-loss Backplane

A 10:4 MUX and 4:10 DEMUX Gearbox LSI for