Kasho Yamamoto

TL;DR: A high-performance annealing processor named STochAsTIc Cellular automata Annealer (STATICA) for solving combinatorial optimization problems represented by fully connected graphs and can update multiple states of fully connected spins simultaneously by introducing different dynamics called stochastic cellular automata annealer.

TL;DR: Annealers exploit the fact that combinatorial optimization problems can be mapped to the ground state search of an Ising model, where the combination of N spins with lowest Ising energy represents the optimal solution to the problem.

TL;DR: A 90nm CMOS 8Gb/s transceiver is developed that achieves a BER of less than 10-12 through a 160cm backplane board with -36.8dB loss at 4GHz and a transceiver power consumption of 232mW.

TL;DR: A flip-flop-based spin circuit allowing expandable bitwidth by reproducing the Metropolis algorithm, which is SA with a fixed temperature, and an inter-chip interface (I/F) with a data-compression method utilizing annealing characteristics to obtain multi-chip operation as discussed by the authors.

TL;DR: The time-division multiplexing Ising machine architecture is proposed that efficiently utilizes on-chip memory resources in an FPGA, in order to address large scale combinatorial optimization problems.