H
Hisashi Kaziwara
Researcher at Hitachi
Publications - 5
Citations - 87
Hisashi Kaziwara is an academic researcher from Hitachi. The author has contributed to research in topics: Multiplier (economics) & Square root. The author has an hindex of 4, co-authored 5 publications receiving 87 citations.
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Patent
Multiplication, division and square root extraction apparatus
Masahisa Narita,Hisashi Kaziwara,Takeshi Asai,Shigeki Morinaga,Hiroyuki Kida,Mitsuru Watabe,Tetsuaki Nakamikawa,Shunpei Kawasaki,Junichi Tatezaki,Norio Nakagawa,Yugo Kashiwagi +10 more
TL;DR: In this paper, a multiplication, division and square root extraction apparatus which calculates the solutions to addition, division, and SE functions by approximation using iteration has a multiplier, an adder-subtracter and a shifter of prescribed bit width connected to a bus.
Patent
Graphic processing system
TL;DR: In this article, a graphic processing system for text display which includes a data processing unit, composed of a memory and a processing unit for creating character code information and a frame buffer for creating pixel information is described.
Patent
System using microprocessor address lines for coprocessor selection within a multi-coprocessor apparatus
Takuichiro Nakazawa,Makoto Hanawa,Atsushi Hasegawa,Ikuya Kawasaki,Kazuhiko Iwasaki,Shigeki Morinaga,Hisashi Kaziwara,Takeshi Asai,Junichi Tatezaki +8 more
TL;DR: In this article, a microprocessor and a number of independent coprocessors for executing individual instructions according to instruction data sent from the microprocessor are connected via an address bus and a data bus.
Patent
System for obtaining strict solution in accordance with accuracy of approximate solutions
Masahisa Narita,Hisashi Kaziwara,Takeshi Asai,Shigeki Morinaga,Hiroyuki Kida,Mitsuru Watabe,Tetsuaki Nakamikawa,Shunpei Kawasaki,Junichi Tatezaki,Norio Nakagawa,Yugo Kashiwagi +10 more
TL;DR: In this paper, a multiplication, division and square root extraction apparatus which calculates the solutions to addition, division, and SE functions by approximation using iteration has a multiplier, an adder-subtracter and a shifter of prescribed bit width connected to a bus.
Patent
Apparatus for multiplication, division and extraction of square root
Masahisa Narita,Hisashi Kaziwara,Takeshi Asai,Shigeki Morinaga,Hiroyuki Kida,Mitsuru Watabe,Tetsuaki Nakamikawa,Shunpei Kawasaki,Junichi Tatezaki,Norio Nakagawa,Yugo Kashiwagi +10 more
TL;DR: A shifter and a calculator connected to a second bus through a switch have a bit width greater than the predetermined bit width, are used for large-scale calculation and prevent a drop in calculation speed as discussed by the authors.