A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.

Method and apparatus for performing multiply-add operations on packed data

A data processing apparatus including a multiplier unit forming a product from L bits of each two data buses of N bits each N is greater than L. The multiplier forms a N bit output having a first portion which is the L most significant bits of the of product and a second portion which is M other bits not including the L least significant bits of the product, where N is the sum of M and L. In the preferred embodiment the M other bits are derived from other bits of the two input data busses, such as the M other bits of the first input data bus. An arithmetic logic unit performs parallel operations (addition, subtraction, Boolean functions) controlled by the same instructions. This arithmetic logic unit is divisible into a selected number of sections for performing identical operations on independent sections of its inputs. The multiplier unit may form dual products from separate parts of the input data. A single instruction controlling both the multiplier unit and the arithmetic logic unit permits addition of dual products. The dual products are temporarily stored in a data register permitting the multiply and add operations to be pipelined. The dual products are formed in one data word and added by a rotate/mask and add operation in a three input arithmetic unit.

Long Instruction Word Controlling Plural Independent Processor Operations

Advertising is marked with a code in a way which makes it difficult to fool the system. The advertising is marked with a code at the time the advertising is produced. Then, when the advertising is broadcast, the code on the advertising is analyzed. Different security measures can be used, including producing the code in the closed captioning so that many different people can see the code, or comparing codes in one part of the signal with a code in another part of the signal. Measures are taken to prevent the code from being used to detect commercials. According to another part of this system, a paradigm for a clearinghouse is disclosed in which the user signs up with the clearinghouse, obtains a line of credit, and the advertiser, the agency, and the ad producer also subscribe to the service. When the ad is actually aired, the payment can be automatically transferred.

Television advertising automated billing system

Input raster image data is divided into objects of each attribute. The division results, and charge information representing a consideration accrued from a vectorized process for the division results are displayed. It is designated whether to execute the vectorized process for the displayed division results. The vectorized process of converting the raster image data into vector data is executed on the basis of the contents of the designation.

Image processing apparatus, control method therefor, and program

A tile-based graphics processing pipeline that uses primitive lists that can encompass plural rendering tiles includes a primitive list reading unit that reads primitive lists for a tile being rendered to determine primitives to be processed for the tile and a rasteriser that rasterises input primitives to generate graphics fragments to be processed. The pipeline further comprises a comparison unit between the primitive list reading unit and the rasteriser that for primitives that have been read from primitive lists that include plural rendering tiles, compares the location of the primitive in the render target to the location of the tile being rendered, and then either sends the primitive onwards to the rasteriser if the comparison determines that the primitive could lie at least partially within the tile, or does not send the primitive to the rasteriser if the comparison determines that the primitive definitely does not lie within the tile.

Method of and apparatus for processing graphics

In a device and system which perform processing, (displaying and outputting) of image data, the amount of data transferred between a memory holding the image data and a processor processing the image data is limited, thereby a great amount of data can be processed at high speed.

Image data processor for processing pixel data in block buffer

PROBLEM TO BE SOLVED: To accelerate printing-out by storing compressed data outputted from a computer, extending these multi-level compressed data synchronously with the output order of print data and transforming them corresponding to printing ability. SOLUTION: The data of image signals at (m) level prepared by an image signal generating part 10 of a computer 1 and stored in an image signal storage part 11 are transmitted to the side of a printer 2 while using a signal transmission part 13 and afterwards, signal processing depending on printer characteristics is executed on the printer side. When the characteristic of a printing part 18 at the printer 2 shows (n) level printing, for example, with the (m) level image signal inputted by a reception part 15 as an object, a level converting part 17 executes signal conversion (m>n) from (m) to (n) corresponding to the printer characteristics. Therefore, a compressing processing part 12 of the computer 1 compresses the image signal while fixing compressibility, an extending processing part 16 of the printer 2 extends this (m) level compressed image signal synchronously with the printing-out order, and the level converting part 17 converts this signal corresponding to the printing ability.

Image processing system.

A multiplication, division and square root extraction apparatus which calculates the solutions to addition, division and square root extraction functions by approximation using iteration has a multiplier, an adder-subtracter and a shifter of prescribed bit width connected to a bus. Iteration is conducted by inputting the output of the multiplier to the adder-subtracter or the shifter and returning the result to the input of the multiplier via the bus. A shifter and an arithmetic and logic unit connected to a second bus connected to the aforesaid bus via a switch have a greater bit width than the prescribed bit width and are used for large scale calculations, thus preventing a reduction in processing speed.

Multiplication, division and square root extraction apparatus

A compact and small compensating-electric-power data processor is realized by dividing a plurality of calculations to be carried out by a complex instruction into a number of executing units to be processed, instead of executing the calculations in parallel as in the past. For this purpose there is provided a decoder having a detecting part for decoding an instruction and for detecting whether the instruction is an instruction for executing a plurality of calculations, a field rearranging part for rearranging a part of the fields of said instruction based on a predetermined number of calculations to be processed if it is judged by said detecting part that the instruction is an instruction for executing a plurality of calculations, and a calculation control part for performing control to execute the calculations in plural cycles in synchronism with the order of said rearranged fields. A calculation part operates to execute the calculations called for by dividing the instruction into plural cycles based on control from the calculation control part.

Data processor for processing a complex instruction by dividing it into executing units

In a device and system which perform processing (displaying and outputting) of image data, the amount of data transferred between a memory holding the image data and a processor processing the image data is limited, thereby a great amount of data can be processed at high speed.

Masahisa Narita

Papers

Image data processor for processing pixel data in block buffer

Image processing system.

Multiplication, division and square root extraction apparatus

Data processor for processing a complex instruction by dividing it into executing units

Image processing device and system using the same