Patent
Multiplication, division and square root extraction apparatus
Masahisa Narita,Hisashi Kaziwara,Takeshi Asai,Shigeki Morinaga,Hiroyuki Kida,Mitsuru Watabe,Tetsuaki Nakamikawa,Shunpei Kawasaki,Junichi Tatezaki,Norio Nakagawa,Yugo Kashiwagi +10 more
TLDR
In this paper, a multiplication, division and square root extraction apparatus which calculates the solutions to addition, division, and SE functions by approximation using iteration has a multiplier, an adder-subtracter and a shifter of prescribed bit width connected to a bus.Abstract:
A multiplication, division and square root extraction apparatus which calculates the solutions to addition, division and square root extraction functions by approximation using iteration has a multiplier, an adder-subtracter and a shifter of prescribed bit width connected to a bus. Iteration is conducted by inputting the output of the multiplier to the adder-subtracter or the shifter and returning the result to the input of the multiplier via the bus. A shifter and an arithmetic and logic unit connected to a second bus connected to the aforesaid bus via a switch have a greater bit width than the prescribed bit width and are used for large scale calculations, thus preventing a reduction in processing speed.read more
Citations
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Patent
Method and apparatus for performing multiply-add operations on packed data
Alexander D. Peleg,Millind Mittal,Larry M. Mennemeier,Benny Eitan,Carole Dulong,Eiichi Kowashi,Wolf Witt +6 more
TL;DR: In this article, a method and apparatus for including in a processor instructions for performing multiply-add operations on packed data is described. But it is not shown how to include such instructions in the instructions themselves.
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References
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Patent
Floating point/integer processor with divide and square root functions
Henry M. Darley,Michael C. Gill,Dale C. Earl,Dinh T. Ngo,Paul C. Wang,Maria B. Hipona,Jim Dodrill +6 more
TL;DR: In this article, a processor (10) with a multiplier array (116), a pipeline register (50), a correction generator (122), and a converter/rounder (52) is described.
Journal ArticleDOI
Some Properties of Iterative Square-Rooting Methods Using High-Speed Multiplication
TL;DR: Three new methods of performing square rooting rapidly which utilize multiplication and no division are presented, considered for convergence rate, efficiency, and implementation.
Journal ArticleDOI
Special Feature an Implementation Guide to a Proposed Standard for Floating-Point Arithmetic
TL;DR: This guide to an IEEE draft standard provides practical algorithms for floating-point arithmetic operations and suggests the hardware/software mix for handling exceptions.
Patent
Floating point circuit with configurable number of multiplier cycles and variable divide cycle ratio
TL;DR: In this paper, an intermediate latch with its own clock is provided at the output of the multiplier half-array in the intermediate stage to feed back data for a second pass for double-precision numbers.
Patent
Method and apparatus for division employing table-lookup and functional iteration
Amdahl G,Clements M +1 more
TL;DR: In this paper, a divide method and a divide apparatus for use in a data processing system are discussed, where a given dividend, No, and a given divisor, Do, are used to calculate a quotient Q. The quotient consists of the quotient bytes Q(O), Q(l),...,Q(i, Q(i+l), etc.