A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.

Method and apparatus for performing multiply-add operations on packed data

A technique for training links in a computing system is disclosed. In one aspect, the technique includes configuring a first receiver in a first port using a first training sequence or a second training sequence; transmitting the second training sequence from the first port indicating the first receiver is configured; and receiving a second training sequence transmitted by a second port at the first port, the second training sequence transmitted by the second port indicating that a second receiver in the second port is configured. In a second aspect, the technique includes locking a communication link; handshaking across the locked link to indicate readiness for data transmission; transmitting information after handshaking across the locked link. And, in a third aspect, the technique includes transmitting a first training sequence from a first port and a second port; and synchronizing the receipt of the first training sequence at the first and second ports; transmitting a second training sequence from the first and second ports upon the synchronized receipt of the first training sequence at the first and second ports; and receiving the second training sequence transmitted by the first and second ports and the second and first ports, respectively, in synchrony.

Method for training a communication link between ports to correct for errors

Systems and methods for providing fast and efficient data compression using a combination of content independent data compression and content dependent data compression. In one aspect, a method for compressing data comprises the steps of: analyzing a data block of an input data stream to identify a data type of the data block, the input data stream comprising a plurality of disparate data types; performing content dependent data compression on the data block, if the data type of the data block is identified; performing content independent data compression on the data block, if the data type of the data block is not identified.

Content independent data compression method and system

To increase the performance of a pipelined processor executing instructions, conditional instruction execution issues and executes instructions, including but not limited to branches, before the controlling conditions may be available and makes the decision to update the destination as late as possible in the pipeline Conditional instruction execution is further improved by a condition code mask field in instructions to choose those condition code bits to be involved in the decision; by a set condition code flag to enable or disable the setting of a condition code; by stale condition code handling to determine if the logically previous conditionally executing instruction was successful or unsuccessful in setting the condition code and to conditionally execute accordingly; by multiple condition codes so that independent instruction sequences can use condition codes in parallel; and by condition code reservation stations to capture a needed condition code as soon as it becomes available and hold that captured value until needed, thus freeing the condition code as soon as possible for use by other instructions Moving the conditional decision from the point of instruction issue to the point of instruction completion permits branch instructions to be eliminated in many cases; permits conditionally executing instructions directly in line; permits filling the branch umbra following a delayed branch with conditionally executing instructions; and reduces the latency from condition code generation to condition code use

Computer processor with an efficient means of executing many instructions simultaneously

A data processing apparatus including a multiplier unit forming a product from L bits of each two data buses of N bits each N is greater than L. The multiplier forms a N bit output having a first portion which is the L most significant bits of the of product and a second portion which is M other bits not including the L least significant bits of the product, where N is the sum of M and L. In the preferred embodiment the M other bits are derived from other bits of the two input data busses, such as the M other bits of the first input data bus. An arithmetic logic unit performs parallel operations (addition, subtraction, Boolean functions) controlled by the same instructions. This arithmetic logic unit is divisible into a selected number of sections for performing identical operations on independent sections of its inputs. The multiplier unit may form dual products from separate parts of the input data. A single instruction controlling both the multiplier unit and the arithmetic logic unit permits addition of dual products. The dual products are temporarily stored in a data register permitting the multiply and add operations to be pipelined. The dual products are formed in one data word and added by a rotate/mask and add operation in a three input arithmetic unit.

Long Instruction Word Controlling Plural Independent Processor Operations

A multiplication, division and square root extraction apparatus which calculates the solutions to addition, division and square root extraction functions by approximation using iteration has a multiplier, an adder-subtracter and a shifter of prescribed bit width connected to a bus. Iteration is conducted by inputting the output of the multiplier to the adder-subtracter or the shifter and returning the result to the input of the multiplier via the bus. A shifter and an arithmetic and logic unit connected to a second bus connected to the aforesaid bus via a switch have a greater bit width than the prescribed bit width and are used for large scale calculations, thus preventing a reduction in processing speed.

Multiplication, division and square root extraction apparatus

A control integrated circuit of the invention is based upon a hierarchical processor structure. A microprogram controller (211) is employed for a high-order processor to give sophisticated functions. A plurality of finite-state transition machines (208, 209) are employed for a low-order processor to increase the speed of operation. The control function for an external input/output device is divided and is executed by a plurality of finite-state transition machines (208,209), the performance thereof being controlled by the microprogram controller (211). According to the present invention, a new control function is processed by adding a finite-state transition machine (210). Namely, the invention provides the general structure of an integrated circuit for controlling various input/output devices.

Control integrated circuit

In an apparatus for decoding cyclic codes generated by a generator polynomial ##EQU1## (where Pi (x) is a mi -order irreducible polynomial) including 0-th to l-th feedback shift registers corresponding to the terms (xc +1) and Pi (x), a coincidence circuit for detecting coincidence of a predetermined number of low order bits of said 0-th to l-th feedback shift registers and all-zero conditions of a high order bits, the predetermined number being a minimum one of numbers of bits (c, m1, m2, . . . ml) of the feedback shift register, the 0-th feedback shift register having an output terminal thereof connected to an input terminal thereof, and the 1st to l-th feedback shift registers each having an output terminal thereof connected to an input terminal thereof and having exclusive OR gates inserted between stages determined by the associated simple polynomial, exclusive OR gates each receiving the output of the associated feedback shift register as one input thereto; a method for decoding the cyclic code for correcting a burst error by shifting the 0-th to l-th feedback shift registers until the coincidence circuit detects the coincidence, comprising the steps of; shifting at least one of said 0-th to l-th feedback shift registers a predetermined number of times; and simultaneously shifting the 0-th to l-th feedback shift registers after the predetermined number of shifting until the coincidence circuit detects the coincidence.

Decoding method and apparatus for cyclic codes

A microcomputer system has a microprocessor and a number of independent coprocessors for executing individual instructions according to instruction data sent from the microprocessor. An address bus and a data bus interconnect the coprocessors with the microprocessor. The microprocessor sends instruction data to the coprocessors via the data bus and concurrently sends coprocessor designation data to the coprocessors via the address bus. The coprocessor designated by the designation data reads and reacts to the instruction data while the other coprocessors within the system disregard the instruction data.

System using microprocessor address lines for coprocessor selection within a multi-coprocessor apparatus

A data buffer is connected to the first and second processor and the first processor sends a start signal to the second processor, which responds to the start signal by reading data from a data source, such as an input/output device, and then writes the read out data into the data buffer. After conclusion of the writing operation, the second processor sends an end signal to the first processor which is admitted to start sending data stored in the buffer to a host processor after receipt of the start signal. The start signal and the end signal are provided to the second processor and the first processor respectively, after passing through a synchronizing circuit.

Junichi Tatezaki

Papers

Multiplication, division and square root extraction apparatus

Control integrated circuit

Decoding method and apparatus for cyclic codes

System using microprocessor address lines for coprocessor selection within a multi-coprocessor apparatus

Data processing system with an enhanced communication control system