This tutorial surveys design methods for energy-efficient system-level design. We consider electronic sytems consisting of a hardware platform and software layers. We consider the three major constituents of hardware that consume energy, namely computation, communication, and storage units, and we review methods of reducing their energy consumption. We also study models for analyzing the energy cost of software, and methods for energy-efficient software design and compilation. This survery is organized around three main phases of a system design: conceptualization and modeling design and implementation, and runtime management. For each phase, we review recent techniques for energy-efficient design of both hardware and software.

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System-level power optimization: techniques and tools

A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.

Method and apparatus for performing multiply-add operations on packed data

Energy consumption is a major concern in many embedded computing systems. Several studies have shown that cache memories account for about 50% of the total energy consumed in these systems. The performance of a given cache architecture is largely determined by the behavior of the application using that cache. Desktop systems have to accommodate a very wide range of applications and therefore the manufacturer usually sets the cache architecture as a compromise given current applications, technology and cost. Unlike desktop systems, embedded systems are designed to run a small range of well-defined applications. In this context, a cache architecture that is tuned for that narrow range of applications can have both increased performance as well as lower energy consumption. We introduce a novel cache architecture intended for embedded microprocessor platforms. The cache can be configured by software to be direct-mapped, two-way, or four-way set associative, using a technique we call way concatenation, having very little size or performance overhead. We show that the proposed cache architecture reduces energy caused by dynamic power compared to a way-shutdown cache. Furthermore, we extend the cache architecture to also support a way shutdown method designed to reduce the energy from static power that is increasing in importance in newer CMOS technologies. Our study of 23 programs drawn from Powerstone, MediaBench and Spec2000 show that tuning the cache's configuration saves energy for every program compared to conventional four-way set-associative as well as direct mapped caches, with average savings of 40% compared to a four-way conventional cache.

/pdf/a-highly-configurable-cache-architecture-for-embedded-9ep56q7ix5.pdf

A highly configurable cache architecture for embedded systems

This paper proposes a new approach using way prediction for achieving high performance and low energy consumption of set-associative caches. By accessing only a single cache way predicted, instead of accessing all the ways in a set, the energy consumption can be reduced. This paper shows that the way-predicting set-associative cache improves the ED (energy-delay) product by 60-70% compared to a conventional set-associative cache,.

Way-predicting set-associative cache for high performance and low energy consumption

Modern microprocessors employ one or two levels of on-chip caches to bridge the burgeoning speed disparities between the processor and the RAM. These SRAM caches are a major source of power dissipation. We investigate architectural techniques, that do not compromise the processor cycle time, for reducing the power dissipation within the on-chip cache hierarchy in superscalar microprocessors. We use a detailed register-level simulator of a superscalar microprocessor that simulates the execution of the SPEC benchmarks and SPICE measurements for the actual layout of a 0.5 micron, 4-metal layer cache, optimized for a 300 MHz, clock. We show that a combination of subbanking, multiple line buffers and bit-line segmentation can reduce the on-chip cache power dissipation by as much as 75% in a technology-independent manner.

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Reducing power in superscalar processor caches using subbanking, multiple line buffers and bit-line segmentation

Hitachi's SH series microprocessors feature 32-bit RISC architecture with a 16-bit, fixed-length instruction set. We describe SH3, a pipelined implementation of the SH architecture with on-chip cache, MMU, and software-programmable power management. Its higher code density and corresponding improvement in instruction-fetch latency lead to higher performance than typical 32-bit RISC architectures achieve. These features, small die size, and low power consumption make SH3 an ideal microprocessor for portable computing systems or multimedia systems.

SH3: high code density, low power

A multiplication, division and square root extraction apparatus which calculates the solutions to addition, division and square root extraction functions by approximation using iteration has a multiplier, an adder-subtracter and a shifter of prescribed bit width connected to a bus. Iteration is conducted by inputting the output of the multiplier to the adder-subtracter or the shifter and returning the result to the input of the multiplier via the bus. A shifter and an arithmetic and logic unit connected to a second bus connected to the aforesaid bus via a switch have a greater bit width than the prescribed bit width and are used for large scale calculations, thus preventing a reduction in processing speed.

Multiplication, division and square root extraction apparatus

In order to divide a memory addressed unidimensionally into a plurality of memory areas and to manage efficiently these memory areas, the address to be accessed inside the memory is determined on a software basis by a computer instruction by use of the value of a first pointer designating each memory area and the value of a second pointer designating the relative address in the designated memory area.

Data processing system having a plurality of register groups and a logical or circuit for addressing one register of one of the register groups

An advanced microprocessor has been developed for the high performance execution of object oriented language programs. In object oriented languages, improvement of frequent or complex operations such as dynamic type checking, procedure calls, and storage management, contributes toward the increase of overall performance. In order to improve their performance, the microprocessor adopts large on-chip register files, a large EPROM for microstore, and ingenious instruction dispatching and tag-handling mechanisms. By specially treating frequently accessed data, i.e., allocating activation records in register files, much of the data traffic can be effectively localized within the chip, and the complexity of procedure calls as well as the burden imposed on storage management can be alleviated. The tag-handling mechanisms efficiently perform dynamic type checking. As the result, the microprocessor, together with an efficient microprogram, executes object oriented language programs much faster than existing computers. Furthermore, it can efficiently execute other high-level languages by using corresponding microprograms, especially AI-languages.

Microprogrammable processor for object-oriented architecture

An address translation apparatus which includes a memory for storing a plurality of physical addresses, and a content addressable memory unit which stores a plurality of signal pairs that correspond to the plurality of physical addresses, each of the signal paris includes a logical address that corresponds to one of the plurality of physical addresses and memory protection level data that indicates a memory protection level allocated to a memory position of the one of the physical addresses. The content addressable memory unit includes apparatus for searching a signal pair that has a logical address in coincident with a logical address being subjected to address translation and comparing memory protection level data to comparative data at a bit position which is indicated to be the bit position to be searched by mask data, in response to the logical address translation. The mask data instructs whether the bits of the stored memory protection level data are to be searched, wherein mask data is determined depending upon a memory access privilege level allocated to a program that requests address translation, and whether comparative data are to be compared with the stored memory protection level data. The content addressable memory further includes apparatus for instructing the memory to produce a physical address that corresponds to the detected signal pair.

Shunpei Kawasaki

Papers

SH3: high code density, low power

Multiplication, division and square root extraction apparatus

Data processing system having a plurality of register groups and a logical or circuit for addressing one register of one of the register groups

Microprogrammable processor for object-oriented architecture

Address translation apparatus having a memory access privilege check capability data which uses mask data to select bit positions of priviledge