Time-Frequency Analysis.

This survey deals with 1/f noise in homogeneous semiconductor samples. A distinction is made between mobility noise and number noise. It is shown that there always is mobility noise with an /spl alpha/ value with a magnitude in the order of 10/sup -4/. Damaging the crystal has a strong influence on /spl alpha/, /spl alpha/ may increase by orders of magnitude. Some theoretical models are briefly discussed none of them can explain all experimental results. The /spl alpha/ values of several semiconductors are given. These values can be used in calculations of 1/f noise in devices. >

1/f Noise Sources

Japanese Journal of Applied Physicsの創刊

This paper presents a concurrent brightness and contrast scaling (CBCS) technique for a cold cathode fluorescent lamp (CCFL) back/it TFT-LCD display. The proposed technique aims at conserving power by reducing the backlight illumination while retaining the image fidelity through preservation of the image contrast. First, we explain how CCFL works and show how to model the non-linearity between its backlight illumination and power consumption. Next, we propose the contrast distortion metric to quantify the image quality loss after backlight scaling. Finally, we formulate and optimally solve the CBCS optimization problem subject to contrast distortion. Experimental results show that an average of 3.7X power saving can be achieved with only 10% of contrast distortion.

/pdf/power-minimization-in-a-backlit-tft-lcd-display-by-1rcqo9jt0n.pdf

Power minimization in a backlit TFT-LCD display by concurrent brightness and contrast scaling

This paper presents a concurrent brightness and contrast scaling (CBCS) technique for a cold cathode fluorescent lamp (CCFL) backlit TFT-LCD display. The proposed technique aims at conserving power by reducing the backlight illumination while retaining the image fidelity through preservation of the image contrast. First, we explain how CCFL works and show how to model the non-linearity between its backlight illumination and power consumption. Next, we propose the contrast distortion metric to quantify the image quality loss after backlight scaling. Finally, we formulate and optimally solve the CBCS optimization problem with the objective of minimizing the fidelity and power metrics. Experimental results show that an average of 3.7X power saving can be achieved with only 10% of contrast distortion.

A dynamic analysis of an amorphous silicon (a-Si) Thin-Film-Transistor-Liquid-Crystal-Display (TFT-LCD) pixel is presented using new a-Si TFT model and new Liquid Crystal (LC) capacitance models for SPICE simulators. This analysis is useful to all Active Matrix LCD designers for evaluating and predicting the performance of LCD's. The a-Si TFT model is developed to simulate important a-Si TFT characteristics such as off-leakage current, threshold voltage shift due to voltage stress and temperature, localized states behavior, and bias- and frequency-dependent gate to-source and gate-to-drain capacitance. In addition, the LC Capacitance model is developed using simplified empirical equations. The modeling procedure is useful to TFT and LCD designers who need to develop their own models. Since our experiments simulate critical TFT-LCD transient effects such as the voltage drop due to gate-to-source capacitance and dynamic off-leakage current, it is possible to accurately characterize TFT-LCD's in the time domain. The analysis and models are applicable to today's optical characterizations of Flat-Panel-Displays (FPD's).

https://www.hpl.hp.com/techreports/96/HPL-96-19.pdf

Dynamic characterization of a-Si TFT-LCD pixels

In this paper, a sensitive and simple technique for parasitic interconnect capacitance measurement with 0.01 fF sensitivity is presented. This on-chip technique is based upon an efficient test structure design. No reference capacitor is needed. Only a DC current meter is required for its measurement. We have applied this technique to extract various interconnect geometry capacitances and compared the results to those from 3D simulations.

An on-chip, interconnect capacitance characterization method with sub-femto-farad resolution

The purpose of this paper is to characterize and model the self-heating effect (SHE) of multifinger n-channel MOSFETs (nMOSFETs). The amount of SHE is small enough not to be analyzed for single-finger bulk CMOS devices. However, SHE should be considered for multifinger nMOSFETs that are mainly used for RF-CMOS applications. The SHE mechanism was analyzed based on a 2-D device simulator. SHE model equations are derived and implemented in the BSIM6 model with Verilog-A language used in a SPICE simulator. The model improves speed and accuracy of multifinger nMOSFETs simulations. To extract thermal resistance and capacitance, an advanced ac conductance method using a vector network analyzer is developed to obtain $I_{{\textrm {ds}}}$ – $V_{{\textrm {ds}}}$ measurement without increasing temperatures with the proposed model and extracted parameters, excellent agreement has been obtained between measurements and simulations in dc and S-parameter domain, whereas the original BSIM6 shows inconsistency between the static dc and the small signal ac simulations due to the lack of SHE. Unlike the widely used subcircuits-based SHE models, including Silicon-On-Insulator MOSFET and power MOSFET models, the proposed SHE model can converge in large-scale circuits even for transient simulations.

Self-Heat Characterizations and Modeling of Multifinger nMOSFETs for RF-CMOS Applications

This paper describes analog/mixed-signal circuit design in the nano CMOS era. Digitally-assisted analog technology is becoming more important, and as an example, our fully digital FPGA implementation of a TDC with self-calibration is shown. Since pure analog circuits are still present and “good” device modeling is required for their designs, device modeling technology for nano CMOS with complicated behavior is also reviewed.

Analog/mixed-signal circuit design in nano CMOS era

In this research accurate capacitance measurement and extraction methods are demonstrated for very thin and large area gate oxide films. We first developed a gate capacitance model which includes any parasitic components and a gate leakage current model, and an interconnect de-embedding procedure which makes accurate measurements possible at the frequency ranges from 100MHz to 4GHz using relatively small gate capacitance TEG's. The target gate capacitance which has large gate area has been finally extracted by using the developed method, SPDC.

Hitoshi Aoki

Papers

Dynamic characterization of a-Si TFT-LCD pixels

An on-chip, interconnect capacitance characterization method with sub-femto-farad resolution

Self-Heat Characterizations and Modeling of Multifinger nMOSFETs for RF-CMOS Applications

Analog/mixed-signal circuit design in nano CMOS era

Leaky large area gate capacitance extraction for nanometer CMOS technology used for RF applications