Wireless power transmission (WPT) is actively being researched and developed. WPT transfers power to electrical load without a wire. One of the problems is that the efficiency is easily affected by load resistance and input power. Therefore, an impedance matching circuit becomes crucial for realization of high-efficiency wireless power systems. In this study, we proposed a maximum power point tracking (MPPT) method for a low-power milliwatt-level RF-dc rectifying circuit using a dc-dc converter. We proposed an RF-dc-dc circuit that consists of an RF-dc rectifier circuit and a dc-dc converter. We measured the RF-to-dc conversion efficiency of the RF-dc-dc circuit using 2.45-GHz microwave power. When the buck-boost converter is connected to the rectifying circuit, the RF-to-dc efficiency of rectifier is approximately steady at 75%, despite the load resistance changing from 100 to 5000 Ω. The overall efficiency of the RF-dc-dc circuit is still over 60%, even though the load resistance varied from 100 to 5000 Ω and the input power changed from 40 to 100 mW.

A Constant Efficiency of Rectifying Circuit in an Extremely Wide Load Range

In this paper, a nonlinear control strategy for controlling a dc/dc buck converter feeding a constant power load is proposed. The main objective of the proposed controller is to improve the transient performance when in presence of unknown power disturbances. A feedback controller is combined with a feedforward strategy. A nonlinear reduced order observer is used for estimating the value of the power load and its time derivative. These estimated values are fed forward to the nonlinear feedback controller whose design is based on feedback linearization method. The proposed controller is tested via simulation and experimental results.

Nonlinear Control of a Buck Converter Which Feeds a Constant Power Load

In this paper, a soft-switching bidirectional dc/dc converter with a LC series resonant circuit is proposed. The proposed converter has been obtained by adding LC series resonant tank in the conventional bidirectional dc/dc converter. The proposed topology performs soft switching at both buck and boost operations. Through the theoretical boost and buck mode analysis, zero voltage switching operation is explained. Moreover, characteristics of the proposed topology are verified with simulation and experimental results.

Soft-Switching Bidirectional DC/DC Converter with a LC Series Resonant Circuit

Granular power delivery with per-core regulation for microprocessor power delivery has the potential to significantly improve the energy efficiency of future data centers. On-chip switched capacitor converters can enable such granular power delivery with per-core regulation given a high efficiency, high power density, fast response time, and high output power converter design. This paper details the implementation of an on-chip switched capacitor voltage regulator in a $32\,\mathrm{n}\mathrm{m}$ SOI CMOS technology with deep trench capacitors. A novel feedforward control for reconfigurable switched capacitor converters is presented. The feedforward control reduces the output voltage droop following a transient load step. This leads to a reduced minimum microprocessor supply voltage, thereby reducing the overall power consumption of the microprocessor. The implemented on-chip switched capacitor voltage regulator provides a $0.7-1.1$ V output voltage from $1.8$ V input. It achieves a $85.1\%$ maximum efficiency at $3.2\,\mathrm{W}\mathrm{/}\mathrm{m}\mathrm{m}^2$ power density, a subnanosecond response time with improved minimum supply voltage capability, and a maximum output power of $10\,\mathrm{W}$ . For an output voltage of $850\,\mathrm{m}\mathrm{V}$ , the feedforward control reduces the required voltage overhead by $60\,\mathrm{m}\mathrm{V}$ for a transient load step from $10\%$ to $100\%$ of the nominal load. This can reduce the overall power consumption of the microprocessor by $7\%$ .

A 10 W On-Chip Switched Capacitor Voltage Regulator With Feedforward Regulation Capability for Granular Microprocessor Power Delivery

A high-efficiency boost dc-dc converter with adaptive peak-inductor-current (APIC) control method is proposed. Besides, a novel two-step startup procedure is also proposed and applied on the boost converter. The proposed integrated boost converter was fabricated by using a 0.18-μm 1P6M mixed-signal process with a die area of 0.96 mm × 0.75 mm, and it is meant to be used with low-power, low-voltage green energy sources and batteries, such as fuel cells, solar cells, and nickel-metal hydride batteries. Hence, the power efficiency, minimal startup voltage, and minimal input voltage are the most important design considerations. The output voltage of the proposed converter is set to 1.8V, and the measured power efficiency is up to 90.6%, occurring when the input voltage is 1.3 V, the output voltage is 1.8 V, and the load current is 50 mA. According to the measured results, the proposed converter can start up successfully with a 0.43-V input voltage. Then, the input voltage can be further lowered to 0.22 V after startup. Moreover, both the efficiency and the output voltage ripple are improved with the proposed APIC method. Furthermore, a two-step startup procedure, which does not require any extra startup assist circuit, is proposed.

Adaptive Peak-Inductor-Current-Controlled PFM Boost Converter With a Near-Threshold Startup Voltage and High Efficiency

This paper presents a precision bandgap reference with an innovative adjusted-temperature-curvature compensation circuit that obtains a good temperature coefficient (TC) over a wide temperature range. The proposed compensation circuit for enhancing the voltage accuracy of the bandgap reference combines an addition circuit, subtraction circuit, and current mirror to achieve an adjusted piecewise linear temperature current over an entire temperature range. The proposed bandgap reference was designed and fabricated using a standard Taiwan Semiconductor Manufacturing Company (TSMC) $0.18~\mu \text{m}$ 1P6M CMOS technology. Measurements on eight samples indicated that the proposed bandgap reference achieved a TC that varies from 1.67 to 10.55 ppm/° from −40 °C to 140 °C with a supply voltage of 1.8 V. The measured 547 mV reference voltage achieved a precision line regulation that is less than 0.08%/V for supply voltages between 1.3 and 1.8 V. The proposed circuit dissipated $28~\mu \text{A}$ with a supply voltage of 1.8 V, and an active area of 0.0094 mm2. The circuit was designed to operate on a low supply voltage down to 1.3 V.

A Sub-1 ppm/°C Precision Bandgap Reference With Adjusted-Temperature-Curvature Compensation

A novel pulse frequency modulation step-up dc-dc converter with maximum power conversion of 9191% and steady-state accuracy of 033% is presented in this letter The high efficiency and exact output are achieved by a dynamic stored energy technique that enhances utility rate of energy with less power consumption This technique uses a dynamic sensing current controller and a load current detector that accurately generates different energy according to various load conditions The boost converter has been designed and fabricated with a standard TSMC 33/5 V 035- mum 2P4M CMOS technology Experimental results show that the output up-ripple voltage variation was 25 mV (61-86 mV), whereas its fixed energy counterpart was 394 mV (86-48 mV) The proposed boost converter has 16% higher power conversion efficiency than the conventional fixed energy technique at 1 mA load current

An Exact Current-Mode PFM Boost Converter With Dynamic Stored Energy Technique

In this study, a precision bandgap reference with a v-curve correction (VCC) circuit is presented. The proposed VCC circuit generates a correction voltage to reduce the temperature drift of the reference voltage and achieves a low temperature coefficient (TC) in a wide temperature range. The proposed bandgap reference was designed and fabricated using a standard TSMC 0.18- $\mu \text{m}$ 1P6M CMOS technology with an active area of 0.0139 mm2. The measured results show that the proposed bandgap reference achieves a TC of 1.9–5.28 ppm/°C over a temperature range of −40°C to 140 °C at a supply voltage of 1.8 V. In addition, the circuit demonstrated a line regulation of 0.033 %/V for supply voltages of 1.2 – 1.8 V at room temperature.

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A High-Precision Bandgap Reference With a V-Curve Correction Circuit

In this paper, a novel start-controlled phase/frequency detector (PFD) for multiphase-output delay-locked loops (MODLLs) is presented. In the proposed PFD, the start-controlled circuit is used to provide a precise multiphase-output without the locking problem. The PFD utilizes a new NAND-resetable dynamic DFF so that a shorter reset path is achieved. Thus, lower power consumption and higher speed can be obtained. A MODLL using the proposed start-controlled PFD is post-layout simulated using the TSMC 0.35-/spl mu/m 2P4M CMOS process. The results show that the total delay time between the input and the output of the MODLL is just one clock cycle and all of the delay cells provide precise multiphase-output without false locking or harmonic locking. Compared to the static DFF based start-controlled PFD, the power consumption of the proposed NAND-resetable dynamic DFF based PFD is reduced at least 61%. The power consumption of the proposed start-controlled PFD is 100 /spl mu/W at 2V and 100MHz. The area of the MODLL circuit is 426 /spl mu/m /spl times/ 381 /spl mu/m.

A novel start-controlled phase/frequency detector for multiphase-output delay-locked loops

Wireless communication technology continues to advance at a rapid pace, and researchers have made tremendous progress in extending single-input single-output (SISO) systems to multiple-input multiple-output (MIMO) systems such as IEEE 802.11n, WiMAX, and LTE. However, a MIMO system requires a detector circuit to separate received data. To reduce the number of comparators required, the method of modified merge sort is proposed, and the results are compared with those of five sorting algorithms. This modified merge sort requires approximately 56% fewer comparators than a bitonic merge sort and approximately 46% fewer comparators than an odd-even merge sort. When implemented in a TSMC 0.18-μm process, the proposed chip demonstrates a throughput of up to 1200 Mbps at an operating frequency of 150 MHz.

Hou-Ming Chen

Papers

A Sub-1 ppm/°C Precision Bandgap Reference With Adjusted-Temperature-Curvature Compensation

An Exact Current-Mode PFM Boost Converter With Dynamic Stored Energy Technique

A High-Precision Bandgap Reference With a V-Curve Correction Circuit

A novel start-controlled phase/frequency detector for multiphase-output delay-locked loops

Implementation of a High-Throughput Modified Merge Sort in MIMO Detection Systems