This paper examines a number of stochastic computational elements employed in artificial neural networks, several of which are introduced for the first time, together with an analysis of their operation. We briefly include multiplication, squaring, addition, subtraction, and division circuits in both unipolar and bipolar formats, the principles of which are well-known, at least for unipolar signals. We have introduced several modifications to improve the speed of the division operation. The primary contribution of this paper, however, is in introducing several state machine-based computational elements for performing sigmoid nonlinearity mappings, linear gain, and exponentiation functions. We also describe an efficient method for the generation of, and conversion between, stochastic and deterministic binary signals. The validity of the present approach is demonstrated in a companion paper through a sample application, the recognition of noisy optical characters using soft competitive learning. Network generalization capabilities of the stochastic network maintain a squared error within 10 percent of that of a floating-point implementation for a wide range of noise levels. While the accuracy of stochastic computation may not compare favorably with more conventional binary radix-based computation, the low circuit area, power, and speed characteristics may, in certain situations, make them attractive for VLSI implementation of artificial neural networks.

Stochastic neural computation. I. Computational elements

The McKinley processor is the result of a joint design effort between Intel and Hewlett-Packard engineers, and is the second processor implementation of the Itanium/sup TM/ processor family (IPF) architecture. This paper describes the methodology developed for testing a complex high-performance microprocessor design. An overview of the processor is presented, along with the goals for the test methodology. Details of the test control blocks, scan methodology, and clocking are given. The scanlatch design, trade-offs and verification processes are discussed, along with some details of ATPG modeling and memory array testing. Finally, some results are presented.

Debug methodology for the McKinley processor

This study provides bridging fault simulation data obtained from the AMD-K6 microprocessor. It shows that: (1) high stuck-at fault coverage (99.5%) implies high bridging fault coverage; (2) coverage of a bridging fault by both wired-AND and wired-OR behavior does not guarantee detection of that fault when compared against a more accurate (transistor-level simulation) modeling method. A set of netname pairs representing bridging fault sites were extracted from layout and used for each fault modeling method. Results show that pattern generation should be driven by the most accurate modeling method when pursuing 100% bridging coverage, since less accurate methods will not necessarily converge to a high quality result.

A comparison of bridging fault simulation methods

In this paper we present the novel built-in delay fault test concepts incorporated into Motorola's MPC7400 PowerPC microprocessor that allow us to use a slow speed tester to do at-speed, scan based, delay fault testing. A novel feature of the design is the programmable clock control circuit for issuing a given number of at-speed clocks for the delay test, once the test is initiated. Using transition and path delay fault test patterns, we have tested several MPC7400 chips at speed exceeding 540 MHz using tester speed of 63 MHz or lower.

At-speed testing of delay faults for Motorola's MPC7400, a PowerPC/sup TM/ microprocessor

The realization of a space-efficient support hardware for built-in self-testing (BIST) is of immense significance in the synthesis of very large scale integration (VLSI) circuits. This paper presents a new zero-aliasing compaction approach of test data outputs with an application specifically targeted to digital embedded cores-based system-on-chips (SOCs), which facilitates the design of such space-efficient BIST support hardware. The suggested technique takes advantage of some well-known concepts of conventional switching theory, together with those of strong and weak compatibilities of response data outputs in the selection of specific gates for merger of an arbitrary but optimal number of output bit streams from the module under test (MUT), based on optimal generalized sequence mergeability, as developed and applied by the authors in earlier works. This is novel in the sense that zero aliasing is realized without any modification of the MUT, while a maximal compaction is achieved in almost all cases in reasonable time utilizing some simple heuristics. The method is illustrated with design details of space compactors for ISCAS 85 combinational benchmark circuits using simulation programs ATALANTA, FSIM, and COMPACTEST, confirming the usefulness of the approach for its simplicity, resulting low area overhead, and full fault coverage for single stuck-line faults, thereby making it suitable in a VLSI design environment. With advances in computational resources in the future, the heuristics adopted in the design algorithm may be further improved upon to significantly lower the simulation CPU time and storage

Space compactor design in VLSI circuits based on graph theoretic concepts

The AMD-K6's embedded design-for-testability structures and test pattern development methodologies provide high-quality manufacturing tests. The DFT features support static voltage-level testing for wafer-sort and debug testing, application of two pattern sequences for detection of timing-related failures, scan-based BIST, and 1149.1 boundary scan.

I.P. Shak

Papers

Testability features of the AMD-K6 microprocessor