Journal ArticleDOI
Testability features of the AMD-K6 microprocessor
R.S. Fetherson,I.P. Shak,S.C. Ma +2 more
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The DFT features support static voltage-level testing for wafer-sort and debug testing, application of two pattern sequences for detection of timing-related failures, scan-based BIST, and 1149.1 boundary scan.Abstract:
The AMD-K6's embedded design-for-testability structures and test pattern development methodologies provide high-quality manufacturing tests. The DFT features support static voltage-level testing for wafer-sort and debug testing, application of two pattern sequences for detection of timing-related failures, scan-based BIST, and 1149.1 boundary scan.read more
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Journal ArticleDOI
Stochastic neural computation. I. Computational elements
B.D. Brown,Howard C. Card +1 more
TL;DR: The primary contribution of this paper is in introducing several state machine-based computational elements for performing sigmoid nonlinearity mappings, linear gain, and exponentiation functions, and describing an efficient method for the generation of, and conversion between, stochastic and deterministic binary signals.
Proceedings ArticleDOI
Debug methodology for the McKinley processor
TL;DR: The McKinley processor is the result of a joint design effort between Intel and Hewlett-Packard engineers, and is the second processor implementation of the Itanium/sup TM/ Processor Family.
Proceedings ArticleDOI
A comparison of bridging fault simulation methods
TL;DR: Results show that pattern generation should be driven by the most accurate modeling method when pursuing 100% bridging coverage, since less accurate methods will not necessarily converge to a high quality result.
Proceedings ArticleDOI
At-speed testing of delay faults for Motorola's MPC7400, a PowerPC/sup TM/ microprocessor
TL;DR: The novel built-in delay fault test concepts incorporated into Motorola's MPC7400 PowerPC microprocessor that allow us to use a slow speed tester to do at-speed, scan based, delay fault testing are presented.
Journal ArticleDOI
Space compactor design in VLSI circuits based on graph theoretic concepts
TL;DR: A new zero-aliasing compaction approach of test data outputs with an application specifically targeted to digital embedded cores-based system-on-chips (SOCs), which facilitates the design of such space-efficient BIST support hardware.
References
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Proceedings ArticleDOI
A logic design structure for LSI testability
TL;DR: A logic design method that will greatly simplify problems in testing, diagnostics, and field service for LSI is described, based on two concepts that are nearly independent but combine efficiently and effectively.
Proceedings ArticleDOI
Fault modeling and test algorithm development for static random access memories
R. Dekker,F. Beenker,L. Thijssen +2 more
TL;DR: Two linear test algorithms (length 9N and 13N respectively, where N is the number of addresses) plus a data retention test are proposed that cover 100% of the faults under the fault model.
Proceedings ArticleDOI
A comparison of defect models for fault location with Iddq measurements
TL;DR: It is shown that Iddq tests may be used for precise diagnosis of defects, using both inter and intra-gate shorts as fault models.
Journal ArticleDOI
An effective BIST scheme for ROM's
Yervant Zorian,André Ivanov +1 more
TL;DR: A built-in self-test (BIST) scheme for ROMs that has very high fault coverage and very small likelihood of error escape (aliasing) is described.
Journal ArticleDOI
An efficient CMOS bridging fault simulator: with SPICE accuracy
C. Di,J.A.G. Jess +1 more
TL;DR: The proposed method can perform very fast bridging fault simulation yet with SPICE accuracy, and experimental results on ISCAS85 benchmarks are promising.