There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality.

Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

I and i

This is an updated version of supplementary information to accompany "Quantum supremacy using a programmable superconducting processor", an article published in the October 24, 2019 issue of Nature. The main article is freely available at this https URL. Summary of changes since arXiv:1910.11333v1 (submitted 23 Oct 2019): added URL for qFlex source code; added Erratum section; added Figure S41 comparing statistical and total uncertainty for log and linear XEB; new References [1,65]; miscellaneous updates for clarity and style consistency; miscellaneous typographical and formatting corrections.

/pdf/supplementary-information-for-quantum-supremacy-using-a-3tkhfafpzk.pdf

Supplementary information for "Quantum supremacy using a programmable superconducting processor"

In this article, we present a small, complete, and efficient SAT-solver in the style of conflict-driven learning, as exemplified by Chaff. We aim to give sufficient details about implementation to enable the reader to construct his or her own solver in a very short time.This will allow users of SAT-solvers to make domain specific extensions or adaptions of current state-of-the-art SAT-techniques, to meet the needs of a particular application area. The presented solver is designed with this in mind, and includes among other things a mechanism for adding arbitrary boolean constraints. It also supports solving a series of related SAT-problems efficiently by an incremental SAT-interface.

/pdf/an-extensible-sat-solver-4r6o94uank.pdf

An Extensible SAT-solver

The promise of quantum computers is that certain computational tasks might be executed exponentially faster on a quantum processor than on a classical processor1. A fundamental challenge is to build a high-fidelity processor capable of running quantum algorithms in an exponentially large computational space. Here we report the use of a processor with programmable superconducting qubits2-7 to create quantum states on 53 qubits, corresponding to a computational state-space of dimension 253 (about 1016). Measurements from repeated experiments sample the resulting probability distribution, which we verify using classical simulations. Our Sycamore processor takes about 200 seconds to sample one instance of a quantum circuit a million times-our benchmarks currently indicate that the equivalent task for a state-of-the-art classical supercomputer would take approximately 10,000 years. This dramatic increase in speed compared to all known classical algorithms is an experimental realization of quantum supremacy8-14 for this specific computational task, heralding a much-anticipated computing paradigm.

/pdf/quantum-supremacy-using-a-programmable-superconducting-5182kq634u.pdf

Quantum supremacy using a programmable superconducting processor

The objective of this paper is to give a comprehensive introduction to applied cryptography with an engineer or computer scientist in mind. The emphasis is on the knowledge needed to create practical systems which supports integrity, confidentiality, or authenticity. Topics covered includes an introduction to the concepts in cryptography, attacks against cryptographic systems, key use and handling, random bit generation, encryption modes, and message authentication codes. Recommendations on algorithms and further reading is given in the end of the paper. This paper should make the reader able to build, understand and evaluate system descriptions and designs based on the cryptographic components described in the paper.

[서평]「Applied Cryptography」

Quantum computers promise to solve important problems faster than conventional computers. However, unleashing this power has been challenging. In particular, design automation runs into (1) the probabilistic nature of quantum computation and (2) exponential requirements for computational resources on non-quantum hardware. In quantum circuit simulation, Decision Diagrams (DDs) have previously shown to reduce the required memory in many important cases by exploiting redundancies in the quantum state. In this paper, we show that this reduction can be amplified by exploiting the probabilistic nature of quantum computers to achieve even more compact representations. Specifically, we propose two new DD-based simulation strategies that approximate the quantum states to attain more compact representations, while, at the same time, allowing the user to control the resulting degradation in accuracy. We also analytically prove the effect of multiple approximations on the attained accuracy and empirically show that the resulting simulation scheme enables speed-ups up to several orders of magnitudes.

As Accurate as Needed, as Efficient as Possible: Approximations in DD-based Quantum Circuit Simulation

The breakdown of Dennard scaling implies radical changes in the design, integration, manufacturing and deployment of new electronic systems. These changes, along with labor-force and macro-economic trends, undermine the status quo in the semiconductor and electronic design automation (EDA) fields. Of particular concern is a fairly static and aging workforce and a decline in new students interested in these fields. Recognizing the dramatic changes afoot, a series of Computing Community Consortium (CCC) sponsored workshops have been organized to identify key steps to take, to secure the future growth of the electronics industry. This paper shares some preliminary findings from the first of these workshops emphasizing challenges in finding and preparing the next generation of electronic design professionals.

“Scaling” the impact of EDA education Preliminary findings from the CCC workshop series on extreme scale design automation

Recent work on differential power analysis shows that even mathematically-secure cryptographic protocols may be vulnerable at the physical implementation level. By measuring energy consumed by a working digital circuit, one can glean enough information to break encryption. Thwarting such attacks requires a new approach to logic and physical design. In this work, we seek to equalize switching activity of a circuit over all possible inputs and input transitions by adding redundant gates and increasing the overall number of signal transitions. We introduce uniformly-switching (U-S) logic, and present a doubling construction that equalizes power dissipation without requiring drastic changes in CAD tools.

/pdf/uniformly-switching-logic-for-cryptographic-hardware-es3g9q9h4t.pdf

Uniformly-Switching Logic for Cryptographic Hardware

The presence of fixed terminals in hypergraph partitioning instances arising in top-down standard-cell placement makes such instances qualitatively different from the free hypergraphs that have driven the past two decades of VLSI CAD partitioning research. In this paper we empirically show that with fixed terminals in the instance, less effort is needed to stably reach a given solution quality. We then develop new benchmark formats that flexibly capture the presence of terminals and any geometric embedding information associated with the partitioning instance. Our new formats not only allow modeling of top-down placement, but also enable study of placement-specific partitioning objectives, e.g., based on net bounding boxes and Steiner tree estimators. Finally, we develop a new suite of partitioning benchmarks with fixed terminals, based on the actual placement data from the IBM-internal circuits released in the ISPD-98 Benchmark Suite [1, 2]. A set of partitioning results is presented with runtime regimes appropriate to the placement use model, as a baseline for future efforts in the research community.

https://web.eecs.umich.edu/~imarkov/pubs/conf/c009.pdf

Partitioning with terminals: a “new” problem and new benchmarks

State elements are increasingly vulnerable to soft errors due to their decreasing size, and the fact that latched errors cannot be completely eliminated by electrical or timing masking. Most prior methods of reducing the soft-error rate (SER) involve combinational redesign, which tends to add area and decrease testability, the latter a concern due to the prevalence of manufacturing defects. Our work explores the fundamental relations between the SER of sequential circuits and their testability in scan mode, and appears to be the first to improve both through retiming. Our retiming methodology relocates registers so that 1) registers become less observable with respect to primary outputs, thereby decreasing overall SER, and 2) combinational nodes become more observable with respect to registers (but not with respect to primary outputs), thereby increasing scan-testability. We present experimental results which show an average decrease of 42% in the SER of latches, and an average improvement of 31% random-pattern testability.

/pdf/improving-testability-and-soft-error-resilience-through-an9hbp0p45.pdf

Igor L. Markov

Papers

As Accurate as Needed, as Efficient as Possible: Approximations in DD-based Quantum Circuit Simulation

“Scaling” the impact of EDA education Preliminary findings from the CCC workshop series on extreme scale design automation

Uniformly-Switching Logic for Cryptographic Hardware

Partitioning with terminals: a “new” problem and new benchmarks

Improving testability and soft-error resilience through retiming