I
Ivan Beretta
Researcher at École Polytechnique Fédérale de Lausanne
Publications - 20
Citations - 297
Ivan Beretta is an academic researcher from École Polytechnique Fédérale de Lausanne. The author has contributed to research in topics: Wireless sensor network & Control reconfiguration. The author has an hindex of 11, co-authored 20 publications receiving 286 citations. Previous affiliations of Ivan Beretta include École Normale Supérieure & Imperial College London.
Papers
More filters
Journal ArticleDOI
A Mapping Flow for Dynamically Reconfigurable Multi-Core System-on-Chip Design
TL;DR: A design flow to efficiently map multiple multi-core applications on a dynamically reconfigurable SoC is presented and is actually able to extract similarities among the applications, as it achieves an average improvement in terms of reconfiguration latency with respect to a communication-oriented approach.
Proceedings ArticleDOI
A high-level synthesis flow for the implementation of iterative stencil loop algorithms on FPGA devices
Alessandro Antonio Nacci,Vincenzo Rana,Francesco Bruschi,Donatella Sciuto,Ivan Beretta,David Atienza +5 more
TL;DR: An automatic design flow to extract parallelism from an ISL algorithm is introduced and a design space exploration is performed to identify its best FPGA hardware implementation, in terms of both area and throughput.
Proceedings ArticleDOI
B²IRS: A Technique to Reduce BAN-BAN Interferences in Wireless Sensor Networks
TL;DR: A BAN-BAN Interference Reduction System (B2IRS) which reschedules beacon packets in order to avoid active period overlap, reducing the interferences between distinct BANs is introduced.
Proceedings ArticleDOI
Hardware/software approach for code synchronization in low-power multi-core sensor nodes
TL;DR: This work proposes a hardware/software approach to synchronize the execution of bio-signal processing applications in multi-core WBSNs, providing the necessary flexibility to execute applications with an arbitrarily large degree of complexity and parallelism, enabling considerable reductions in power consumption for all multi- core WBSN execution conditions.
Journal ArticleDOI
A Mapping-Scheduling Algorithm for Hardware Acceleration on Reconfigurable Platforms
TL;DR: This article proposes a novel task representation model, named Temporal Constrained Data Flow Diagram (TCDFD), which aims at minimizing the dynamic reconfiguration overhead while meeting the communication requirements among the tasks and presents a mapping-scheduling algorithm that is able to take advantage of the new TCDFD model.