A data storage device such as a DRAM memory having a plurality of data storage cells (10) is disclosed. Each data storage cell (10) has a physical parameter which varies with time and represents one of two binary logic states. A selection circuit (16), writing circuits (18) and a refreshing circuit (22) apply input signals to the data storage cells to reverse the variation of the physical parameter with time of at least those cells representing one of the binary logic states by causing a different variation in the physical parameter of cells in one of said states than in the other.

Data storage device and refreshing method for use with such device

A technique of sampling, sensing, reading and/or determining the data state of a memory cell (of, for example, a memory cell array) including an electrically floating body transistor In this regard, the intrinsic bipolar transistor current component is employed to read and/or determine the data state of the electrically floating body memory cell During the read operation, the data state is determined primarily by or read (or sensed) substantially using the bipolar current component responsive to the read control signals and significantly less by the interface channel current component, which is negligible relative to the bipolar component The bipolar transistor current component may be very sensitive to the floating body potential due to the high gain of the intrinsic bipolar transistor of the electrically floating body transistor As such, the programming window obtainable with this reading technique may be considerably higher than the programming window employing a conventional reading technique (which is based primarily on the interface channel current component)

Bipolar reading technique for a memory cell having an electrically floating body transistor

An integrated circuit device comprising a memory cell array having a plurality of memory cells arranged in a matrix of rows and columns; multiplexer circuitry, coupled to the memory cell array, comprising a plurality of data multiplexers, each data multiplexer having a plurality of inputs, comprising (i) a first input to receive write data which is representative of data to be written into the memory cells of the memory cell array in response to a write operation, and (ii) a second input to receive read data which is representative of data read from memory cells of the memory cell array, and an associated output to responsively output data from one of the plurality of inputs; and syndrome generation circuitry, coupled to the multiplexer circuitry, to generate: (i) a write data syndrome vector using the write data and (ii) a read data syndrome vector using the read data.

Integrated circuit having memory array including ECC and column redundancy and method of operating same

In one embodiment to the invention, a semiconductor circuit includes a substrate and a first well formed in the substrate. A first group of field effect transistors is formed in the first well and has a first body. The circuit includes a first body voltage to the first body to forward body bias the first group of field effect transistors. The circuit includes a first isolation structure to contain the first body voltage in the first well. In another embodiment, the circuit further includes a second group of field effect transistors having a non-forward body bias and the first isolation structure prevents the first body voltage from influencing a voltage of a body of the second group of field effect transistors. In yet another embodiment, a second isolation structure adjacent to the second well contain a second body voltage in a second well holding the second group of field effect transistors.

Multiple well transistor circuits having forward body bias

An integrated circuit device (e.g., a logic device or a memory device) having a memory cell array which includes (i) a plurality of memory cells, wherein each memory cell is programmable to store one of a plurality of data states, and (ii) a bit line, having a plurality of memory cells coupled thereto. Memory cell control circuitry applies one or more read control signals to perform a read operation wherein, in response to the read control signals, a selected memory cell conducts a current which is representative of the data state stored therein. Sense amplifier circuitry senses the data state stored in the selected memory cell using a signal which is responsive to the current conducted by the selected memory cell. Current regulation circuitry is responsively and electrically coupled to the bit line during a portion of the read operation to sink or source at least a portion of the current provided on the bit line. Sensing circuitry responsively couples the current regulation circuitry to the bit line during the portion of the read operation.

Read circuitry for an integrated circuit having memory cells and/or a memory cell array, and method of operating same

Previous conflicting reports concerning fully depleted SOI device hot electron reliability may result from overestimation of channel electric field (E/sub m/). Experimental results using SOI MOSFET's with body contacts indicate that E/sub m/ is just a weak function of thin-film SOI thickness (T/sub si/ and that E/sub m/ can be significantly lower than in a bulk device with drain junction depth (X/sub j/) comparable to SOI's T/sub si/. The theoretical correlation between SOI MOSFET's gate current and substrate current are experimentally confirmed. This provides a means (I/sub G/) of studying E/sub m/ in SOI device without body contacts. Thin-film SOI MOSFET's have better prospects for meeting breakdown voltage and hot-electron reliability requirements than previously thought. >

Hot-carrier effects in thin-film fully depleted SOI MOSFET's

We have investigated the ability of high and low temperature anneals to repair the gate oxide damage due to simulated electrical stress caused by wafer charging resulting from plasma etching, etc. Even 800/spl deg/C anneal cannot restore the stability in interface trap generation. Even 900/spl deg/C anneal cannot repair the deteriorated charge-to-breakdown and oxide charge trapping. As a small consolation, the ineffectiveness of anneal in repairing the process-induced damage allows us to monitor the damages even at the end of the fabrication process. >

Effect of low and high temperature anneal on process-induced damage of gate oxide

PMOS transistors with effective channel lengths down to 0.15 mu m have been fabricated on silicon-on-insulator (SOI) films. Gate oxide thicknesses of 5.5 and 10 nm are used. These P/sup +/ gate PMOS devices exhibit excellent short-channel behavior, low-source-drain resistance, and remarkably large current drive and transconductance. for T/sub ox/=5.5 nm, saturation transconductances of 274 mS/mm at 300 K and 352 mS/mm at 80 K are achieved, which are the highest reported values for this oxide thickness. The result is attributed to low series resistance, forward-bias body effect, and the reduction of body charge effect. >

J.C. King

Papers

Hot-carrier effects in thin-film fully depleted SOI MOSFET's

Effect of low and high temperature anneal on process-induced damage of gate oxide

High-performance sub-quarter-micrometer PMOSFET's on SOI