Showing papers in "IEEE Electron Device Letters in 1994"

Electron mobility enhancement in strained-Si n-type metal-oxide-semiconductor field-effect transistors

Abstract: Enhanced performance is demonstrated in n-type metal-oxide-semiconductor field-effect transistors with channel regions formed by pseudomorphic growth of strained Si on relaxed Si/sub 1/spl minus/x/Ge/sub x/ Standard MOS fabrication techniques were utilized, including thermal oxidation of the strained Si Surface channel devices show low-field mobility enhancements of 80% at room temperature and 12% at 10 K, when compared to control devices fabricated in Czochralski Si Similar enhancements are observed in the device transconductance In addition, buried channel devices show peak room temperature mobilities about three times that of control devices >

Performance limiting micropipe defects in silicon carbide wafers

Abstract: Reports on the characteristics of a major defect in mass-produced silicon carbide wafers which severely limits the performance of silicon carbide power devices. Micropipe defects originating in 4H- and 6H-SiC substrates were found to cause pre-avalanche reverse-bias point failures in most epitaxially-grown pn junction devices of 1 mm/sup 2/ or larger in area. Until such defects are significantly reduced from their present density (on the order of 100's of micropipes/cm/sup 2/), silicon carbide power device ratings will be restricted to around several amps or less. >

A dynamic threshold voltage MOSFET (DTMOS) for very low voltage operation

Abstract: A new mode of operation for Silicon-On-Insulator (SOI) MOSFET is experimentally investigated. This mode gives rise to a Dynamic Threshold voltage MOSFET (DTMOS). DTMOS threshold voltage drops as gate voltage is raised, resulting in a much higher current drive than regular MOSFET at low V/sub dd/. On the other hand, V/sub t/ is high at V/sub gs/=0, thus the leakage current is low. Suitability of this device for ultra low voltage operation is demonstrated by ring oscillator performance down to V/sub dd/=0.5 V. >

Monolithic NMOS digital integrated circuits in 6H-SiC

Abstract: We report the first digital monolithic integrated circuits in the wide bandgap semiconductor silicon carbide (SiC). These logic gates are implemented in enhancement-mode NMOS using ion implanted MOSFET's with non-self-aligned metal gates. We have fabricated and characterized inverters, NAND and NOR gates, XNOR gates, D-latches, RS flip-flops, binary counters, and half adders. All circuits operate properly from room temperature to over 300/spl deg/C. >

Ultrafast operation of V/sub th/-adjusted p/sup +/-n/sup +/ double-gate SOI MOSFET's

Abstract: To optimize the V/sub th/ of double-gate SOI MOSFET's, we fabricated devices with p/sup +/ poly-Si for the front-gate electrode and n/sup +/ poly-Si for the back-gate electrode on 40-nm-thick direct-bonded SOI wafers. We obtained an experimental V/sub th/ of 0.17 V for nMOS and -0.24 V for pMOS devices. These double-gate devices have good short-channel characteristics, low parasitic resistances, and large drive currents. For gates 0.19 /spl mu/m long, front-gate oxides 8.2 nm thick, and back-gate oxides 9.9 nm thick, we obtained ring oscillator delay times of 43 ps at 1 V and 27 ps at 2 V. To our knowledge, these values are the fastest reported for this gate length with suppressed short-channel effects. >

Ti-Si-N diffusion barriers between silicon and copper

Abstract: Thin films of Ti-Si-N, reactively spattered from a Ti/sub 5/Si/sub 3/ target, are assessed as diffusion barriers between silicon substrates and copper overlayers. By tests on shallow-junction diodes, a 100 nm Ti/sub 34/Si/sub 23/N/sub 43/ barrier is able to prevent copper from reaching the silicon substrate during a 850/spl deg/C/30 min anneal in vacuum. A 10 nm film prevents diffusion up to 650/spl deg/C/30 min. By high-resolution transmission electron microscopy, Ti/sub 34/Si/sub 23/N/sub 43/ predominantly consists of nanophase TiN grains roughly 2 nm in size. >

A simple edge termination for silicon carbide devices with nearly ideal breakdown voltage

Abstract: In this paper, a simple edge termination is described which can achieve near ideal parallel plane breakdown for silicon carbide devices. This novel edge termination involves self aligned implantation of a neutral species on the edges of devices to form an amorphous layer. With this termination formed using argon implantation, the breakdown voltage of Schottky barrier diodes was measured to be very close to ideal plane parallel breakdown voltage. >

Improved charge control and frequency performance in InAs/AlSb-based heterostructure field-effect transistors

Abstract: We demonstrate high-speed InAs/AlSb-based heterostructure field-effect transistors (HFET's) displaying greatly improved charge control properties and enhanced high-frequency gate performance. Microwave devices with a 0.5/spl times/84 /spl mu/m/sup 2/ exhibit a peak unity current gain cut-off frequency of f/sub T/=93 GHz. The HFET usable operational range was extended to V/sub DS/=1.5 V (from V/sub DS/=0.4-0.5 V) thus greatly enhancing the applicability of InAs/AlSb-based HFET's for low-power, high-frequency amplification. We also report on the bias dependence of f/sub T/, and demonstrate that InAs/AlSb-based HFET's offer an attractive frequency performance over an adequately wide range of drain biases. >

Suppression of boron penetration in p/sup +/ polysilicon gate P-MOSFETs using low-temperature gate-oxide N/sub 2/O anneal

Abstract: It has been reported that high-temperature (/spl sim/1100/spl deg/C) N/sub 2/O-annealed oxide can block boron penetration from poly-Si gates to the silicon substrate. However, this high-temperature step may be inappropriate for the low thermal budgets required of deep-submicron ULSI MOSFETs. Low-temperature (900/spl sim/950/spl deg/C) N/sub 2/O-annealed gate oxide is also a good barrier to boron penetration. For the first time, the change in channel doping profile due to compensation of arsenic and boron ionized impurities was resolved using MOS C-V measurement techniques. It was found that the higher the nitrogen concentration incorporated at Si/SiO/sub 2/ interface, the more effective is the suppression of boron penetration. The experimental results also suggest that, for 60/spl sim/110 /spl Aring/ gate oxides, a certain amount of nitrogen (/spl sim/2.2%) incorporated near the Si/SiO/sub 2/ interface is essential to effectively prevent boron diffusing into the underlying silicon substrate. >

Deep-submicrometer channel design in silicon-on-insulator (SOI) MOSFET's

Abstract: Short-channel effects in deep-submicrometer SOI MOSFET's are explored over a wide range of device parameters using two-dimensional numerical simulations. To obtain reduced short-channel effects in SOI over bulk technologies, the silicon film thickness most be considerably smaller than the bulk junction depth because of an additional charge-sharing phenomenon through the SOI buried oxide. The optimal design space, considering nominal and short-channel threshold voltage, shows ample design options for both fully and partially depleted devices, however, manufacturing considerations in the 0.1 /spl mu/m regime may favor partially depleted devices. >

0.10 /spl mu/m graded InGaAs channel InP HEMT with 305 GHz f/sub T/ and 340 GHz f/sub max/

Abstract: We report here 305 GHz f/sub T/, 340 GHz f/sub max/, and 1550 mS/mm extrinsic g/sub m/ from a 0.10 /spl mu/m In/sub x/Ga/sub 1-x/As/In/sub 0.62/Al/sub 0.48/As/InP HEMT with x graded from 0.60 to 0.80. This device has the highest f/sub T/ yet reported for a 0.10 /spl mu/m gate length and the highest combination of f/sub T/ and f/sub max/ reported for any three-terminal device. This performance is achieved by using a graded-channel design which simultaneously increases the effective indium composition of the channel while optimizing channel thickness. >

Scaling-parameter-dependent model for subthreshold swing S in double-gate SOI MOSFET's

Abstract: We derived a simple formula for the subthreshold swing S in double-gate (DG) SOI MOSFET's. Our formula, which depends only on a scaling device parameter, matches the device simulation results. From these results, our equations are simple and give a scaling rule for DG-SOI MOSFET's. >

Hot-carrier effects in thin-film fully depleted SOI MOSFET's

Abstract: Previous conflicting reports concerning fully depleted SOI device hot electron reliability may result from overestimation of channel electric field (E/sub m/). Experimental results using SOI MOSFET's with body contacts indicate that E/sub m/ is just a weak function of thin-film SOI thickness (T/sub si/ and that E/sub m/ can be significantly lower than in a bulk device with drain junction depth (X/sub j/) comparable to SOI's T/sub si/. The theoretical correlation between SOI MOSFET's gate current and substrate current are experimentally confirmed. This provides a means (I/sub G/) of studying E/sub m/ in SOI device without body contacts. Thin-film SOI MOSFET's have better prospects for meeting breakdown voltage and hot-electron reliability requirements than previously thought. >

MOS characteristics of ultrathin NO-grown oxynitrides

Abstract: In this paper, we report for the first time, the growth of high quality ultrathin oxynitrides formed by nitridation of SiO/sub 2/ in nitric oxide (NO) ambient using in-situ rapid thermal processing (RTP). This process is highly self-limited compared with N/sub 2/O oxidation of silicon. A significant improvement in the interface endurance and charge trapping properties, under constant current stress, compared to pure O/sub 2/-grown and N/sub 2/O-grown oxides is observed. The NO growth process will have a great impact on future CMOS and EEPROM technologies. >

4H-SiC MESFET with 2.8 W/mm power density at 1.8 GHz

Abstract: MESFET's were fabricated using 4H-SiC substrates and epitaxy The DC, S-parameter, and output power characteristics of the 07 /spl mu/m gate length, 332 /spl mu/m gate width MESFET's were measured At /spl nu//sub ds/=25 V the current density was about 300 mA/mm and the maximum transconductance was in the range of 38-42 mS/mm The device had 93 dB gain at 5 GHz and f/sub max/=129 GHz At V/sub ds/=54 V the power density was 28 W/mm with a power added efficiency=127% >

Contact and via structures with copper interconnects fabricated using dual Damascene technology

Abstract: A novel submicron process sequence was developed for the fabrication of CoSi/sub 2//n/sup +/-Si, CoSi/sub 2//p/sup +/-Si ohmic contacts and multilevel interconnects with copper as the interconnect/via metal and titanium as the diffusion barrier. SiO/sub 2/ deposited by plasma enhanced chemical vapor deposition (PECVD) using TEOS/O/sub 2/ was planarized by the novel technique of chemical-mechanical polishing (CMP) and served as the dielectric. The recessed copper interconnects in the oxide were formed by chemical-mechanical polishing. (dual Damascene process). Electrical characterization of the ohmic contacts yielded contact resistivity values of 10/sup -6//spl Omega/-cm/sup 2/ or less. A specific contact resistivity value of 1.5/spl times/10/sup -8//spl Omega/-cm/sup 2/ was measured for metal/metal contacts. >

HEMT degradation in hydrogen gas

Abstract: The effect of hydrogen treatment on both GaAs pseudomorphic HEMT's and InP-based HEMT's, in order to simulate the hermetic seal environment in a Kovar package, is reported for the first time. Under the 270/spl deg/C, 4% H/sub 2/ in Ar atmosphere, significant changes in both types of HEMT's were observed within several minutes. While the drain current at a fixed gate bias and the pinchoff voltage of the GaAs PHEMT consistently decreased under the influence of the hydrogen gas, they were found to either increase or decrease with the InP HEMT. The change of device characteristics resulting from exposure to the hydrogen environment is not permanent; partial recovery of device characteristics was observed under either nitrogen or hydrogen at both elevated and room temperatures. The change in HEMT DC characteristics seems to be primarily resulted from the change in the gate built-in potential. Any device changes due to the Si-donor neutralization by atomic hydrogen, and therefore a reduction in channel carrier concentration, were found to be insignificant. >

P-N double quantum well resonant interband tunneling diode with peak-to-valley current ratio of 144 at room temperature

Abstract: The current-voltage characteristics of the P-N double quantum well resonant interband tunneling (RIT) diodes in InAlAs-InGaAs system have been improved in this letter. The peak-to-valley current ratio (PVCR) is as high as 144 at room temperature. As we know, this is the highest room temperature PVCR ever reported in any tunneling devices. Moreover, the influence of the central barrier thickness varying from 10 /spl Aring/ to 30 /spl Aring/ on the device characteristics is also studied. >

Effect of low and high temperature anneal on process-induced damage of gate oxide

Abstract: We have investigated the ability of high and low temperature anneals to repair the gate oxide damage due to simulated electrical stress caused by wafer charging resulting from plasma etching, etc. Even 800/spl deg/C anneal cannot restore the stability in interface trap generation. Even 900/spl deg/C anneal cannot repair the deteriorated charge-to-breakdown and oxide charge trapping. As a small consolation, the ineffectiveness of anneal in repairing the process-induced damage allows us to monitor the damages even at the end of the fabrication process. >

Impact ionization in InAlAs/InGaAs HFET's

Abstract: The presence of an energy barrier to the transfer of holes from the channel to the gate electrode of InAlAs/InGaAs HFET's prevents the gate current from being a reliable indicator of impact ionization. Consequently, we have used a specially designed sidegate structure to demonstrate that due to the narrow bandgap of InGaAs, impact ionization takes place in the channel of these devices under normal operating conditions. The ionization coefficient was found to follow a classic exponential dependence on the inverse electric field at the drain end of the gate, for over three orders of magnitude. >

RF performance of SiC MESFET's on high resistivity substrates

Abstract: State-of-the art SiC MESFET's showing a record high f/sub max/ of 26 GHz and RF gain of 8.5 dB at 10 GHz are described in this paper. These results were obtained by using high-resistivity SiC substrates for the first time to minimize substrate parasitics. The fabrication and characterization of these devices are discussed. >

Recessed-channel structure for fabricating ultrathin SOI MOSFET with low series resistance

Abstract: A new recessed-channel SOI (RCSOI) technology has been developed for fabricating ultrathin SOI MOSFET's with low source/drain series resistance. Thin-film fully depleted SOI MOSFET's with channel film thickness of 72 nm have been fabricated with the RCSOI technology. The new structure demonstrated a 70% reduction in source/drain series resistance compared with conventional processes. In the deep-submicron region, more than 80% improvement in saturation drain current and transconductance over conventional devices was achieved using the RCSOI technology. The new technology would also facilitate the use of silicide for further reducing the series resistance. >

An efficient method for plasma-charging damage measurement

Abstract: The initial slope of the voltage versus time curve during constant current stressing of gate-oxide has been demonstrated, for the first time, as a good indicator for plasma-charging damage. This method of damage measurement measures the charge trapping rate of the gate-oxide directly while it is under a high-field stress. It combines the stressing and measuring steps in one rapid measurement. Using only capacitors as testing vehicle, this method does not require extensive processing. Using current stressing instead of CV measurement, this method greatly reduces the measurement time and the size requirement of the capacitor. The ability of this measurement method in bringing out the passivated defects after annealing is demonstrated. An example of using this method in detecting plasma-charging damage is included. >

Experimental high performance sub-0.1 /spl mu/m channel nMOSFET's

Abstract: Very high performance sub-0.1 /spl mu/m channel nMOSFET's are fabricated with 35 /spl Aring/ gate oxide and shallow source-drain extensions. An 8.8-ps/stage delay at V/sub dd/=1.5 V is recorded from a 0.08 /spl mu/m channel nMOS ring oscillator at 85 K. The room temperature delay is 11.3 ps/stage. These are the fastest switching speeds reported to date for any silicon devices at these temperatures. Cutoff frequencies (f/sub T/) of a 0.08 /spl mu/m channel device are 93 GHz at 300 K, and 119 GHz at 85 K, respectively. Record saturation transconductances, 740 mS/mm at 300 K and 1040 mS/mm at 85 K, are obtained from a 0.05 /spl mu/m channel device. Good subthreshold characteristics are achieved for 0.09 /spl mu/m channel devices with a source-drain halo process. >

A simple EEPROM cell using twin polysilicon thin film transistors

Abstract: A planar twin polysilicon thin film transistor (TFT) EEPROM cell fabricated with a simple low temperature (/spl les/600/spl deg/C) process is demonstrated in this work. The gate electrodes of the two TFT's are connected to form the floating gate of the cell, while the source and drain of the larger TFT are connected to form the control gate. The cell is programmed and erased by Fowler-Nordheim tunneling. The threshold voltage of the cell can be shifted by as much as 8 V after programming. This new EEPROM cell can dramatically reduce the cost of production by reducing manufacturing complexity. >

Hot-carrier induced electron mobility and series resistance degradation in LDD NMOSFET's

Abstract: The mobility and the series resistant degradation of LDD NMOSFET's were determined independently for the first time. Three device structures with different styles of drain engineering: 1) modestly doped LDD; 2) large-angle-tilt implanted drain, and 3) buried LDD were studied. We observed clearly that the series resistant drift dominates the initial device degradation and the relative importance of the mobility degradation increases as the stress time proceeds. Our work provides a useful guideline for device reliability optimization and for the development of the device degradation model for the circuit reliability simulation. >

Thermally and electrically isolated single crystal silicon structures in CMOS technology

Abstract: Thermally and electrically isolated single crystal silicon structures have been fabricated using a post-processing anisotropic tetramethyl ammonium hydroxide (TMAH) electrochemical etch. The process was carried out on CMOS circuits fabricated by a commercial foundry. Since the etch consists of a single micromachining step performed on packaged and bonded dice, this technique has the potential for cost-effective prototyping and production of integrated sensors and circuits. >

Breakdown voltage improvement for thin-film SOI power MOSFET's by a buried oxide step structure

Abstract: Numerical simulations are performed to demonstrate that a new SOI power MOSFET structure, namely buried oxide step structure (BOSS), introduces a high electric field peak near the buried oxide step and that this peak reduces the height of the other electric field peaks within thin silicon layer. The relaxation of these peaks results in higher breakdown voltages at much higher impurity concentrations than those in the conventional structure. >

Mobility-field behavior of fully depleted SOI MOSFET's

Abstract: This work reports measured effective mobility vs. effective vertical electric field and the accompanying experimental method of extraction for the fully depleted (FD) SOI MOSFET. The effective channel mobility vs. effective vertical electric field behavior was investigated as a function of the SOI film doping concentration, the SOI back-gate bias, and the SOI film thickness. The validity of using the approximation, Q/sub i/=C/sub ox/(V/sub GS//spl minus/V/sub TH/), for the inversion charge density in FD SOI is examined and experimentally confirmed. >

Trench doping conformality by plasma immersion ion implantation (PIII)

Abstract: Plasma immersion ion implantation (PIII) is a technique which can be used to conformally dope sidewalls of Si trenches. Using junction staining techniques and subsequently calibrating the observed stained depth to measured dose, dopant distributions inside Si trenches with aspect ratios ranging from 1 to 12 are studied for various bias voltages from 5 to 20 kV. Unlike conventional collimated beam implantation, PIII was able to conformally dope all aspect ratios studied with no evidence of abrupt discontinuities in the dopant distribution along the trench surface as a result of beam shadowing by trench geometry. Furthermore, it is shown that the higher implant biases results in more directional trajectories. Thus, dopant distributions along irregular geometries can be controlled by PDIII process conditions. >